VIKAS SINGH

Flat No. - **D, Sai Apartment, Block-B2, Sec.-71

Noida, Uttar Pradesh Pin:-201301

Phone No.:- +91-880*******, +91-982*******

Email ID:- actedk@r.postjobfree.com

CAREER OBJECTIVE

Looking for a prospect where technical competencies are valued and I can make a meaningful contribution to the growth of a company and be a part of technical innovation during my service.

ACEDEMICS

STANDARD

YEAR

BOARD

SCHOOL/UNIVERSITY

MARKS M.TECH (VLSI DESIGN)

2014

SGVU

SURESH GYAN VIHAR UNIVERSITY

64

B.TECH. (ELECTRONICS AND COMMUNICATION)

2012

SGVU

SURESH GYAN VIHAR UNIVERSITY

71

12th

2007

CBSE

BIRLA SENIOR SECONDARY SCHOOL

71

10th

2005

RBSE

ETERNAL LIFE SECONDARY SCHOOL

54

TECHINICAL SKILLS

HDL/HVL: - VHDL, Verilog HDL, System Verilog

Software Languages:-C, C++, MATLAB

Tools/Packages:-Microsoft Office, Xilinx ISE 14.1i

Hardware: - FPGA SPARTAN-3 XC3S200, FPGA SPARTAN-6 XC6S50, CPLD XC9500

Simulator: - Model Sim 5.4a, ISIM Simulator, Questa Sim 10.0b

Methodology :- Introductory UVM

PROFESSIONAL INTERSHIP

VLSI Front End Designing and Verification

Completed internship program of 6 months in VLSI DESIGN from an organization i.e. CETPA INFOTECH PVT. LTD. There I have worked on Designing, Verification and Hardware Implementation using Verilog HDL, System Verilog and FPGA/CPLD

PROJECTS IN INTERNSHIP

Object 1: - Booth Multiplier

Brief: -This project was produced as Minor project. This multiplier performs the multiplication of two signed binary numbers in two's complement notation. This is the fastest method of multiplication.

Tools & Environment: -Verilog HDL, Xilinx ISE 14.1, ISIM/ModelSim, FPGA SPARTAN-3

Object 2: -Orthogonal Code Convolution for Efficient Digital Communication

Brief: - This project was produced as Major project. This method is quite useful in digital communication. Orthogonal code is one of the best methods in detecting and correcting the error to provide better communication.

Tools & Environment: - Verilog HDL, Xilinx ISE 14.1i, ISIM/ModelSim, SPARTAN-6

Object 3: -Designing &Verification of FIFO

Brief: - FIFOs are widely used in logic design for buffering, queuing and management of rate, priorities and flow control in data applications. A FIFO consists of a read pointer and a write pointer, pointing to entries in a storage array typically, made of flip-flops.

Tools & Environment: - Verilog HDL, System Verilog, Xilinx ISE 14.1i, QUESTA SIM

Object 4: -Designing & Verification of RAM

Brief: - RAM is a type of computer memory that can be accessed randomly; that is; any byte of memory can be accessed without touching the preceding bytes. RAM is the most common type of memory found in computers and other devices, such as printers.

Tools & Environment: - Verilog HDL, System Verilog, Xilinx ISE 14.1i, QUESTA SIM

INDUSTRIAL TRAINING

BHEL EDN BANGALORE, INDIA:- Training was conducted by Bangalore office in a production plant in which we were given a particular exposure on various departments such as Semiconductors, SCADA, HDVC, PCB assembling and testing, MAX DNA, Turbines, Photovoltaic, Energy Meters (June 6, 2011-July 6, 2011).

PUBLISHED THESIS WORK

Thesis Object: - ELIMINATION OF GAUSSIAN NOISE USING VARIOUS FILTERING METHODOLIGES

About:-To remove Gaussian noise from an image, Weiner filter is preferred but it doesn’t the satisfactory results. Its output is a blur image. To remove this drawback, I have designed a new filter which operates on Wavelet transform technique. In this technique, the image to be de-noised get decomposed into small wavelets, remove noise from each wavelet and finally recomposed it. The final result is checked in terms of PSNR and its visual performance.

PROJETS IN ENGINEERING

Object 1:-8-Digit Codes Lock for Appliance Switching

Brief: - This project was produced as Major project. For this project, we were 3 members. This code lock is useful for appliances requiring authorized use by those who know the preset code. And if desired, the code can be changed.

Object 2:-Live Wire Detector

Brief: - This project was produced as Minor project. For this project, we were 2 members. This detector is useful in finding the exact breaking point in power cables which happens due to mechanical stress and strain on cables due the use of portable loads for a long period.

EXTRA CURRICULAR ACTIVITES

Core member of ‘Student Placement Cell’ of my college.

Part of core co-ordination team of ‘X-animo-11’ a national level cultural festival organized by my college.

DECLARATION

I, hereby, declare that all the information provided by me in this resume is verified and correct.

Vikas Singh

Place: -

Date: -

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