ARSHMEET KAUR

Design & Verification Engineer at

InfoSemi Technologies Pvt. Ltd.

987-***-****(M)

actcyi@r.postjobfree.com

CAREER OBJECTIVE

To carve out an eminent position with a leading institution by dint of my knowledge, aptitude and interpersonal skills. I hold a positive outlook and an unrelenting attitude so that I can tackle any situation with reason and intellect. SUMMARY

Presently working as Design and Verification Engineer at InfoSemi Technologies Pvt. Ltd. Noida since October 2014

Worked on AMBA AXI VIP

Worked for Skill Development Project under Government Of India (UDAAN

– for J&K youth)

Assisted in Verification Plan preparation

Verification using System Verilog in UVM

Constrained Random and Assertion-based verification

RTL Designing using Verilog HDL

Worked as Design & Verification Intern at Tevatron Technologies Pvt. Ltd. Noida from December 2013 to September 2014

RTL Designing using Verilog & VHDL

Verification using System Verilog in VMM

Worked on Basic Protocols – I2C, UART, Arbiter Design System

Explored RTL development techniques

Worked on FPGA (Digilent Spartan-3E board)

Completed graduation (B.TECH, EEE) from GGSIPU in August 2013 EDUCATIONAL QUALIFICATION

B.TECH (Electrical and Electronics Engineering) (2009-2013) from Guru Tegh Bahadur Institute of Technology, GGSIPU.

Aggregate Percentage: 70.80%

All India Senior School Certificate Examination (Class XII, CBSE) (2009) from K.V. Tagore Garden, New Delhi.

Aggregate Percentage: 83.6%

All India Secondary School Examination (Class X, CBSE) (2007) from K.V. Tagore Garden, New Delhi.

Aggregate Percentage: 91.8%

KEY SKILLS

Languages - Verilog, System Verilog, VHDL

Verification Methodologies – VMM, directed & random constraints stimuli, assertion based verification, coverage driven verification, UVM.

Softwares and Tools worked on – Model Sim, NC Sim, Questa Sim, Xilinx, Yosys, GOF, Icarcus Verilog, Gtkwave.

Operating Systems worked on - Redhat, Linux, Windows. Basic knowledge in FPGA (Spartan3E), C, C++

Basic know-how of Synthesis, Timing analysis

Basic understanding of LAYERED PROTOCOL ARCHITECTURE Knowledge of BASIC PROTOCOLS – I2C, UART, AMBA AXI3, APB TRAINING

NTPC Limited (June 2012 to August 2012)

SKH Metals Ltd (Maruti Joint Venture) (June 2012 to July 2012)

Knix Solutions (Embedded Systems) (June 2011 to August 2011)

Basic Electronics Training conducted by Sailor Enterprises (June 2010 to July 2010)

CERTIFICATIONS

Undergoing online course of ‘Essentials of Professional VLSI Digital Design’ by

‘Logosent Semiconductors India Pvt. Ltd.’

PROJECTS

Working on implementation of a ‘PWM IP with industry standard AMBA APB interface and programmable period/duty cycle’.

Working on AMBA AXI3 Protocol, VIP development using UVM in System Verilog Roles & Responsibilities:

Test Plan preparation

Creation of testbench environment

Master Agent

Implementation of ‘SHIFT PATTERN DETECT Design with a counter triggered on pattern detect’.

Gate-level implementation of designs by synthesis using TSMC018 standard cell library.

FIFO implementation using Verilog.

Worked on Design and Verification of I2C BUS PROTOCOL in team of 2 members:

Micro-architecture

Prototype level of designing using Verilog

Verification in Verilog and System Verilog (VMM)

Project on ARBITER DESIGN SYSTEM in Verilog

Micro-architecture

RTL Designing & Verification in Verilog

Assisted in white-paper work

Worked on UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER

(UART) Protocol in Verilog

Design & Verification of Four-Port Switch

Design & Verification of Timer module

Project on DIGITAL ACCESS CONTROL SYSTEM in Verilog

Project on VENDING MACHINE in VHDL

Worked on STATE MACHINE and SEQUENCE DETECTORS

Project on HOME AUTOMATION ( Used Embedded C for programming of the microcontroller ) (2011)

Energy Audit of Transformers.

Study on UREA FUEL CELL.

Project on DIGITAL DATA TRANSFER BY AN OPTICAL FIBRE.

Project on SOLAR INVERTER

ACCOMPLISHMENTS

Contributed towards Skill Development by conducting Technical Sessions and Lab Sessions in VLSI domain for a project under Government Of India named

‘UDAAN’ on behalf of InfoSemi Technologies Pvt. Ltd.

Assisted in White Paper Work of project ‘ARBITER DESIGN SYSTEM’ for Tevatron Technologies Pvt. Ltd.

Event Coordinator of ‘Paper presentation Event’ in National Student Convention 2011

Volunteer ship in an event (AD-MAD) in College Fest.

Wall Magazine Artist of TRANSISTORZ (TZ) SOCIETY (Technical Society of GTBIT).

Editorial board member for school magazine.

SKILLS AND INTERESTS

Efficient at coordinating and management.

Good at rapport building, empathetic, good communication skills.

Good at motivating people, enhancing positive thinking.

Optimistic towards my own life and goals.

Knack of life skills.

Leadership qualities.

Reading and Net browsing.

PERSONAL PROFILE

Date of Birth: 15-JAN-1991

Nationality : Indian

Father’s name: Lt. Mr. P.S. Anand

Permanent Address: C-160 ’A’,F.F, Mansarover garden, New Delhi-110015

Language Known: English, Hindi

Hobbies: Listening Music, Reading Books, Net Surfing DECLARATION :

I hereby declare that the details provided by me in this resume are correct. I am aware that the company can use this data for verification purposes Date: Place: New Delhi Signature: Arshmeet Kaur

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