CANDACE CONTRERAS

acszhy@r.postjobfree.com 602-***-**** Mesa, AZ

Semiconductor Layout Design Engineer

Accomplished, results-driven, and performance-focused professional with proven track record for success utilizing Cadence Virtuoso, while maximizing available resources. Recognized as a multi-disciplined, forward-looking leader; encompasses futuristic thinking and vision; develops strategies, procedures to drive appropriate layouts while effectively troubleshooting for maximum efficiency. High bias for action, organized, and process oriented approach that has provided proven business results and solid team performance.

KEY STRENGTHS

Project Management and Design

Technical Expertise

Troubleshooting

Complete projects on time or ahead of schedule

Forecasting/Analysis

Diagnostics

PROFESSIONAL EXPERIENCE

Layout Design Engineer 2015-present

Independent Contractor

Kelly Services

Cactus Semiconductor

Teacher's Assistant, Integrated Circuit Design Class 2015

Mesa Community College Mesa, AZ

Assist students with Cadence Virtuoso labs and exercises. Performs general administrative tasks such as filing, record-keeping; maintain records and compile varied reports in an accurate and timely manner.

Layout Design Engineer 2011-2014

SeaVision, Inc. Chandler, AZ

Lead layout designer, responsible for layout from top level down; led projects into completion and on time. Managed project scheduling; top level floor plan. Pad ring development, pixel cell creation, standard cell development. Successfully created and implemented standard logic for company use. Performed strict verification check on pattern layout (e.g. DRC, LVS, antenna, density). Interacted with designers regarding design issues and requests for design improvements. Revised existing layout designs to meet the required specifications.

Layout Designer 2007-2011

Maxim Integrated Products Chandler, AZ

Extensive block and cell experience; created layouts optimized for space. Followed and adhered to strict ESD and latch-up guidelines for automotive applications; created standard logic for department use. Presented technical discussion and design review after the completion of any layout design. Communicated and cooperated with teammates and designers to analyze floor plans and complex circuits, solved existing problems, and delivered all projects successfully on time; archived project databases and documents for back up.

ON THE JOB EXPERIENCE

Analog and mixed-signal layout DFM

Experienced in 65-180nm

TSMC, SMIC and company specific design processes

Power management

Understanding of induced parasitic prevention of substrate current injection.

Planning, layout and verification of analog and mixed signal CMOS and BiCMOS IC's

Low voltage (3 to 5 volts), High voltage (18 to 75 volts)

Processes: Twin tub, double poly, four metal designs using two major processes each with three variations

EDUCATION

Analog Integrated Circuit Design, 2007

Digital Integrated Circuit Design, 2006

Mesa Community College, Mesa, AZ

Major in Human Nutritional Studies, 2006

Arizona State University, Mesa, AZ

Associates in Applied Sciences, 2002

Mesa Community College, Mesa, AZ

TECHNICAL PROFICIENCIES

Cadence Virtuoso, VXL, LTL and L-Edit layout editors

Calibre, Assura, Dracula and L-Edit verification tools to run DRC, LVS, LPE, ERC, antenna and density checks

PC and Unix proficient

Microsoft and Open Office Products

SKILLS

Analytical self-starter with experience in process improvement, technical problem solving, and cross-functional team work across diverse disciplines.

Displays Conflict Resolution, Critical Thinking, Team Objectives, Compliance, and Communication.

Ability to analyze and provide strategic solutions to ensure successful outcomes. Successful in both independent and shared work environments.

Anticipates and understands company needs and goals; manages and communicates with team members effectively.

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