RESUME

SWATI G. SALUNKE

Current Address:

Nitheesha PG Hostel No. 70, R J garden,

Anand nagar, opposite to kalamandir, Mobile: +919********* Back side of dominos pizza, marathahalli, Email: acspht@r.postjobfree.com Bengaluru - 560037, Karnataka in.linkedin.com/pub/swati-salunke/9b/7a5/505 CAREER OBJECTIVE:

To be associated with a progressive organization that provides an opportunity to apply and enhance my knowledge and skills in the field of VLSI Design / ASIC / Verification. EDUCATIONAL DETAILS:

Examination College/University Year of

passing

CGPA/ Percentage

M.Tech.

(VLSI Design)

Visvesvaraya National Institute of

Technology, Nagpur

June 2015 8.55

B.E.

(Electronics

&Telecommunication)

Government College of Engineering,

Aurangabad

June -2012 8.75

HSC Yogeshwari Mahavidyalaya,Ambajogai June-2008 82.33% SSC Smt.G.K.Y.K.School,Ambajogai June-2006 83.86%

ACADEMIC PROJECTS:

M.Tech Project:

Project Title: Formal Verification of Load-Store unit of OpenSPARC T1 Processor Description: Here we have used assertion based formal verification approach to verify Load- Store unit of OpenSPARC T1 processor. Here the design intent of a Load-Store unit is captured in terms of property in an executable, formal, unambiguous manner and then these properties are verified using IFV tool. The assertion language and tool we used are PSL (property specification language) and IFV (Incisive Formal Verifier) respectively.

B.E. Project:

Project Title: DC carrier communication

Description: In this technology, we have tried to use the DC power supply lines to pass the communication signal between different devices i.e. different devices can communicate with each other using DC power supply lines instead of using separate wires for Communication. Mini Projects:

Design of single ended CMOS Differential Amplifier: For a given specifications, designing and simulation was done using Cadence Virtuoso Tool then the layout designing, DRC, LVS, RCX and parasitic (post) simulation checks were performed. Finally the results of without parasitics (pre) and with parasitics (post layout) simulation were compared and variations in the simulated values were observed. For layout designing we have used the same Cadence Virtuoso Tool and 180nm Technology file. FPGA implementation of Digital Clock:

In this short term project entire structural level VHDL code was written for the digital clock. The entire code was written and synthesized in the tool Xilinx ISE. The correctness of the code was verified through simulation and also by dumping the code in the FPGA (Virtex-II). The power analysis was done in the Xpower Analyzer by Xilinx.

PUBLICATION :

Ankush Nikam, Swati Salunke, Sweta Bhurse. (2015, March). Design and Implementation of 32 bit Complex Multiplier using Vedic Algorithm, in International Journal of Engineering Research & Technology, 2015, ISSN: 2278- 0181, Vol. 4

TECHNICAL SKILLS:

Languages :- C, VHDL, Verilog, SPICE, PLC.

Software Tools :- Matlab, Sentaurus TCAD, Cadence, Mentor graphics Eldo, Modelsim/Xilinx, NgSpice, Comsol4.3a, IFV (Incisive Formal Verifier), LATEX. Operating system :- Linux, Windows 7.

TRAINING AND EXPERIENCE:

Done a training at VIDEOCON industries Ltd. In quality control department.

Done a short term course of study in PLC Programming at INDO GERMAN TOOL ROOM

(MSME),Aurangabad (An ISO 9001:2008, ISO 14001:2004 and BS OHSAS 18001:2007 Institution)

Done a Corporate Soft Skills Diploma in ISO 9001- 2008 Certified Training Centre.

Attended INUP familiarization workshop on Nanofabrication Technologies held at IIT Bombay, Mumbai during 26-28 May 2014.

ACHIEVEMENTS:

3rd prize winner in inter-college paper presentation competition held at J.N.E.C., Aurangabad.

Runner up in intra-college cricket match held at VNIT,Nagpur.

1st prize winner in intra-college dance competition held at Govt. College of Engg., Aurangabad. EXTRA-CURRICULAR ACTIVITIES:

Organized event WINGS 10 held at Govt. college of Engg.,Aurangabad

Active participation in various sports and cultural activities.

Organizer for various college level events.

PERSONAL PROFILE:

Name : Swati G. Salunke

Date of Birth : 29th May 1991

Gender : Female

Nationality : Indian

Mother Tongue : Marathi

Languages Known : English, Hindi & Marathi.

Permanent Address : Om Shanti Colony, Laxmi Nivas, Ambajogai, Maharashtra- 431517 . DECLARATION:

I hereby declare that all the above information are true and correct to best of my knowledge. Date:

Place: Nagpur Swati G. Salunke

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