MITHRA CHANDRAN

Email: acspaq@r.postjobfree.com

Phone: 997-***-****

Career Objective

Looking for the position of analog/digital circuit design engineer.

Skills

Extensive knowledge of SRAM memory cell circuit design techniques.

Experience in transistor level circuit design.

Good understanding of semiconductor processing.

Strong passion for technology.

Designed various combinational, complex gates and flip-flops.

Experience in assisting circuit design in 0.18um to 28nm CMOS processes technologies

Good understanding of device physics

Proven Analog/Mixed signal/RF IC and digital circuit design skills.

Solid understanding of MOSFET electrical characteristics.

Good understanding of Electro-migration, ESD and Latch up.

Strong research and analytic skills

Fluent in written and spoken English.

Excellent in presentation and interpersonal communication skills.

Excellent in technical troubleshooting and demonstrated problem solving skills

Eager, quick learner with strong team-work spirit.

Ready to relocate.

Work Experience

Research Assistant

Organization: Dept. of Electrical and Computer engineering, University of Colorado at Colorado springs Duration: January 2009 to January 2010

Performed the tasks of optimizing schematics

Transistor level circuit design and simulation

Graduate assistant at University of Colorado, Colorado springs from August 2006 to December 2008

Project trainee at Hindustan Newsprint Limited, India, for 5 months in 2005

2010-2014 Career break for taking care of my children

Education

1.Master’s degree (MS) in Electrical and Computer Engineering, University of Colorado at Colorado Springs, CO, USA

Graduation date: December 2009 Cumulative GPA: 3.4/4.0

Thesis: Power Integrity issues and on chip decoupling capacitors

2.B.Tech (Bachelor of Technology) Applied Electronics and Instrumentation, Mount Zion College of Engineering (Mahatma Gandhi University), Kerala State, India.

Graduated- May 2005 67.37%

Relevant Projects

1.64 bit CMOS SRAM circuit (8 inputs for the 8 bits, 3-bit address, RE/WE signals, 1.2V, TSMC 0.12um)

2.24-bit Full Adder design in TSMC 0.13um technology.

3.Design and layout of D flip flop and JK filp flops.

4.8-bit Current Steering Digital to Analog Converter (DAC) in TSMC 0.25um technology.

5.PLL with charge-pump phase comparators (Kvco=100MHz/V, Kpd=1V/rad, Vdd=3V, fLPF=1MHz, fin=100MHz, TSMC 0.25um)

6.6-bit flash A/D converter with interpolation/folding circuits (100MS/s, Vdd=-Vss=3V, TSMC 0.12um)

7.Fully differential folded-cascode opamp (Gain=53dB, w-3dB=30kHz, SR=0.25 mV/us, TSMC 0.25um)

8.Second-order Delta-Sigma Modulator; second-order MASH modulator using two first-order modulators (1 bit, data rate=10MHz, Vdd=5V)

9.RF filters (low pass, high pass and band pass)

Technical skills

CAD tools: Cadence, HSPICE, Microwind layout tool, RFsim

Lab Equipment’s: Oscilloscope, Network Analyzer, Spectrum Analyzer.

HDL languages: Verilog (beginner)

Programming Languages: C programming, Assembly language 8085

Operating systems: UNIX, Windows NT/XP, Linux, DOS, Matlab/Simulink

Proficient in MS Excel, MS Word and MS PowerPoint.

Relevant Courses works

CMOS digital integrated circuits

VLSI processing

Analog IC design

Systems on Chip architecture

Mixed Signal IC design

Computer architecture and design

RF IC design

Operating Systems

Affiliations and Professional activities

Volunteered in grading graduate student’s course work in the Electrical and Computer engineering dept. at University of Colorado.

Society for Women Engineers (SWE) member

International students association, University of Colorado

References

1.Dr. Dan, Dean of Electrical and Applied sciences, UCCS. acspaq@r.postjobfree.com Phone: +1-719-***-****.

2.Dr. T.S. Kalkur, Dept. Chairperson, Dept. of ECE, UCCS. acspaq@r.postjobfree.com Phone:+1-719-***-****

Contact this candidate