MOHANA.R

Contact No: +91-897**-***** Site #**,Mallappa layout,

Email ID: acslsl@r.postjobfree.com Virgo Nagar Post,

Seegehalli,

K.R.Puram,

Bangalore-49.

Objective

To get prominent in the discipline assigned by exploring my skill sets and work to the best of my ability for the benefit of the concern.

Academic Performance

S.No

Course Studied

Year of Passing

Name of the Institution

Board/

University

Percentage of Marks

1.

M.TECH

VLSI Design

2013

Sathyabama University

Deemed University

8.99 CGPA

2.

B.E. ECE

2009

Paavai Engineering College

Anna University

78.00%

3.

HSC

2005

Sri Vani Matric Higher Secondary School

State Board

90.83%

4.

SSLC

2003

Sri Vani Matric Higher Secondary School

Matric Board

86.63%

Area Of Interest

VLSI Design

Digital electronics

Microprocessor-8085

Project Profile

FPGA IMPLEMENTATION OF REVERSIBLE BIDIRECTIONAL BARREL SHIFTER

In this work the FPGA implementation of the reversible logic based barrel shifter for low-area delay buffer is presented. The reversible logic based barrel shifter is designed using the Fredkin, Feynman gates and FF gate using XILINX tool. The simulation is done using the Model SIM simulator and the transient analyses are done using different inputs. The synthesis is done using the XST and the synthesis report, timing report are analyzed. The different analysis like delay, number of gates for the Fredkin, Feynman gates and proposed FF gate are obtained. The design of the barrel shifter using the existing and proposed gate is compared in terms of number of gates used to realize the system and speed in terms of the delay. For high speed applications the barrel shifters become more popular which can shift and rotate multiple bits in a single cycle.

Work Experience

P.G.P Engineering and Technology as Lecturer Sep 2009 to Jun 2011

Responsibilities:-

I have handled Digital Electronics, VLSI design, Electronic circuits, Microprocessor & Microcontroller & respective Labs.

Carry out regular teaching and practical classes as per prescribed guidelines

Teaching methods include lectures, seminars and practical laboratory demonstrations

Exam cell coordinator at department level

Participate in setting question papers, conducting examinations, assess work and provide feedback to students

Provide timely guidance and feed back to students, advice and counsel them

Contribute to the management of quality, audit and other external assessments

Technical Skills

Operating System : Windows 98, 2000/XP, MS DOS

Languages : Programming in HDL (VHDL, Verilog HDL), Basics of C

Web Technologies : HTML

Tools : PSPICE, HSPICE, Microwind (layout tool)

Achievements

Obtained university 3rd Rank in overall M.Tech VLSI Design(2013)

Got 2nd Rank in III Semester in the department.

Secured 1st mark in Advanced Digital Signal & Image processing.

Extra / Co-Curricular Activities

Won the first place in Zonal level Football match.

Won the third place in intra-college Throw ball match.

Received many prizes during intra-school athletic meet.

Won the first place twice in intra-school dance competition

Worked as Class Representative.

Personal Details

Father’s Name : M.Rajendran

Date of Birth : 27th April 1988

Personal Status : Female/Married

Hobbies : Solving Sudoku, Driving.

Languages Known : English, Tamil

Declaration

I hereby declare that all the information furnished above is true to the best of my knowledge.

Place : Signature

Date : (R.MOHANA)

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