RESUME

Mr. NAYAN KUMAR NAWARE

Local Address Permanent Address

Opposite S.G.S. College, 625/D Goriya Plot

Madahalli Old Madras Road, Amanpur, Madan

Bangalore, Mahal, Jabalpur,

Karnataka, Madhya Pradesh

Pin - 560049 Pin - 482003

Mobile No. : +919********* Email: acsllj@r.postjobfree.com Date Of Birth : 22/08/1990

Summary :

Highly motivated, creative, versatile professional seeking challenging career in a highly esteemed organization that gives me a platform to use my expertise skills for mutual growth and benefit of organization and myself. Currently undergoing Advance Verification Training at Smart Chip Design Bangalore.

Educational Qualification:

Degree College University Year %/CGPA

M.E.

(IV sem)

PIMPRI CHINCHWAD

COLLEGE OF ENGG.

PUNE UNIVERSITY 2015 Dissertation

Submitted

Result

Awaiting

M.E.

(III sem)

PIMPRI CHINCHWAD

COLLEGE OF ENGG.

PUNE UNIVERSITY 2015 7.6

M.E.

(II sem)

PIMPRI CHINCHWAD

COLLEGE OF ENGG.

PUNE UNIVERSITY 2014 8.0

M.E.

(I sem)

PIMPRI CHINCHWAD

COLLEGE OF ENGG.

PUNE UNIVERSITY 2013 8.2

B.E. TAKSHSHILA INSTITUTE

OF TECHNOLOGY

RGPV University

BHOPAL

2012 75.72

T.E. TAKSHSHILA INSTITUTE

OF TECHNOLOGY

RGPV University

BHOPAL

2011 71.9

S.E. TAKSHSHILA INSTITUTE

OF TECHNOLOGY

RGPV University

BHOPAL

2010 64.45

F.E. TAKSHSHILA INSTITUTE

OF TECHNOLOGY

RGPV University

BHOPAL

2009 64.00

H.S.C. JOY SENIOR SECONDARY

SCHOOL JABALPUR

C.B.S.E 2008 50.33

S.S.C. JOY SENIOR SECONDARY

SCHOOL JABALPUR

C.B.S.E 2006 69.00

Software Skills :

Programming Language: VHDL, Verilog, System Verilog, OVM, UVM, C and C++, OOPs, Shell scripting, Python, SPICE Circuit Simulation. Tools: Xilinx ISE 14.2, Tanner 15.0, Mentorgraphics (Questasim, Pyxis & Leonardo), ModelSim, Microwind, Matlab, System Generator, Chips Co Pro, Simulink, Latex.

Hardware Platform :

SPARTAN 6 NEXYS 3, Vertex 5, Raspberry Pi.

Project Work:

1. IP level verification using System Verilog OVM and UVM methodologies. 2. Design of 16x1 Quaternary Look Up Table using CAM cells. (M.E. Project) This project deals with the design of Quaternary Logic blocks for Look Up Table implementation. Quaternary logic provide four levels 0,1,2,3 represented by Gnd, 1/3Vdd, 2/3 Vdd and Vdd. Quaternary LUT is designed using five 4x1 MUX in two stage whose select line is define by DLC circuit. To the input of each MUX a CAM cell is attached instead of SRAM cell. The project is designed and simulated using TANNER Tool v15 (S-edit, T-spice, E-wave) using PTM 180nm Technology file.

3. FPGA based Partial Reconfigurable Adaptive QAM implementation for new generation wireless systems.

In this project different variants of QAM are designed using Simulink blocks as well as using system generator block. VHDL code from system generator block set is downloaded in Vertex5 FPGA that support Partial Reconfiguration features. By providing the channel conditions to FPGA switching between different QAM variants will be done automatically. 4. Architecture for filtering images using Xilinx System Generator. This project presents architecture for filters pixel by pixel and regions filters for image processing using Xilinx System Generator (XSG). This architecture offer an alternative through a graphical user interface that combines MATLAB, Simulink and XSG and explore important aspects concerned to hardware implementation. 5.Image Segmentation on Raspberry Pi.

In this project image segmentation is done using color space model and threshold on Raspberry Pi using Python Language.

6. Child Safety management using RF ID Technology. (B.E. Project) This project provides the safety measures with the help of Radio Frequency. This system helps to locate child, pets or things which usually run out of sight. An RF ID Tag (433Mhz) attached and are provided with a code which is continuously transmitted to base station. Base station is controlled using AT89c51 Microcontroller and Cypress CYWUSB6935 containing a 2.4-GHz radio transceiver, GFSK modem, and a dual DSSS reconfigurable baseband. As these RF ID tag move beyond certain range (that can be adjusted) the base station is alarmed.

Vocational Trainings and Workshops :

1) ASIC Advance Verification training at Smart Chip Design Bangalore. 2) Four weeks training at BHARAT RATNA BHIM RAO AMBEDKAR INSTITUTE OF TELECOM TRAINING CENTER Ridge Road, Jabalpur 482001. (26 June – 26 July, 2011).

3) Two weeks training at BHARAT SANCHAR NIGAM LTD. Jabalpur M.P.

(13 July – 27 July, 2010).

4) Four weeks training on 8051 Microcontroller and Embedded system from AIMS INTERACRIVE Pvt. Ltd. Jabalpur.(01 Feb – 01 March,2010). 5) Three days workshop on B-Robotix by MINDSTEIN TECH SOLUTIONS at Takshashila Institute of Technology Jabalpur M.P. (3-5 Feb,2011). 6) Three days workshop on Design of Antenna and Hands on FEKO tool at Takshshila Institute of Technology Jabalpur M.P. (9-11 May 2011). Papers / Journals :

1. Nayan Kumar Naware, Dr. Sheetal Bhandari, Varsha Bendere, CNTFET Based logic Circuit : A brief review. Presented at TECHNOVISION International Conference 2014 Sihgadh Inst. of technology Pune. Volume 5 Issue 2 March 2014. 2. Nayan Kumar Naware, D.S.Khurge, Dr. Sheetal Bhandari, Review of Quaternary Algebra & its Logic Circuits ICCUBEA International Conference 2015 Pimpri Chinchwad College of Engineering Pune 27th Feb 2015. 3. Nayan Kumar Naware, Priyanka Waniya, A brief review on Single Electron Transistor, International Journal on Emerging Trends in Technology (IJETT)ISSN: 2350 – 0808, Volume 2, Issue 1, April- 2015.

4. Nayan Kumar Naware, D.S.Khurge, Dr. Sheetal Bhandari, Review on Content Addressable Memory Architecture, International Journal on Emerging Trends in Technology (IJETT)ISSN: 2350 – 0808, Volume 2, Issue 1, April- 2015. Conferences :

ICCUBEA 2015 First International Conference on Computing, Communication, Control And Automation 26 -27 Feb 2015 at PCCOE Pune.

27th International conference on VLSI Design 2014 at IIT Bombay.

TECHNOVISION international Conference 2014 Sihgadh Inst. of technology Pune.

EPGCON 2014 National Conference at K.K.Wagh Institute of technology Nasik.

EPGPEX 2015 National Level Project Exhibition at AISSMS IOT, Pune. Membership :

VSI Society of India. (Membership No. 20133123)

Extra Curricular :

First Prize in Paper Presentation at PG level in TECHLLIGENT-14, a national level Symposium at PCCOE, Pune.

First Prize in Poster Presentation at PG level in TECHLLIGENT-14, a national level Symposium at PCCOE, Pune.

Represented Jabalpur at State Level Basket Ball Competition 2003, 2004, 2005.

Won Interschool Basket Ball Competition 2006.

Active member of Art of Living and active participation in Social activities and charity. Strengths :

Punctual and Discipline.

Team leading Capabilities.

Hard Working and Dedicated.

Good Communication Skills.

Hobbies :

Playing guitar, Basket Ball, Yoga, Music, Reading motivational books. Lingual Dexterity :

Hindi, Marathi, English.

Learning French

Declaration :

I hereby declare that the information given to the company is correct to the best of my knowledge and belief.

Place:

Date: / / NAYAN KUMAR NAWARE

Contact this candidate