Mallikarjun S Bankapur

#***/*, **** * **** road, 24th cross,

HSR Layout, sector-3,Bangalore Email : acsksb@r.postjobfree.com Karnataka, India – 560102 Mobile: +91-996*******

Summary of Qualifications

Good understanding of the ASIC and FPGA design flow

Extensive experience in writing RTL models in Verilog HDL and Test benches in System Verilog and UVM

Very good knowledge in verification methodologies

Experience in using industry standard EDA tools for the front-end design and verification

Knowledge of Perl Script and Linux Makefile

VLSI Domain Skills

HDL: Verilog

HVL: System Verilog

Verification Methodologies: Coverage Driven Verification Assertion Based Verification - SVA

TB Methodology: UVM

Protocols: SPI, UART, GPIO

EDA Tool: Questasim and ISE

Domain: ASIC/FPGA front-end Design and Verification Knowledge: RTL Coding, FSM based design, Simulation, Code Coverage, Functional Coverage, Synthesis,

Static Timing Analysis, ABV- SVA

Professional Qualification

Maven Silicon Certified Advanced VLSI Design and Verification course from Maven Silicon VLSI Design and Training Center, Bangalore June 2015 – Oct 2015.

M.Tech. in Signal Processing and VLSI from Jain University, Bangalore, 2013 (aggregate 85.92%) B.E. Electronics and communication from, S.C.T.I.T. affiliated to Vishveswaraya Technological University, Belgaum,2011(Aggregate - 70.96% )

Achievements

Secured 1st Rank in final semester in engineering.

Secured 4th Rank in M.Tech.

Received “Best Boy” award during 10th std.

State Level “Science Chintana Exam” winner.

Experience

Design Engineer, Maven Silicon, Six months experience in front end design and verification. June 2015 – present.

VLSI Projects

[1] Router 1x3 – RTL design and Verification

HDL: Verilog

HVL: System Verilog

TB Methodology: UVM

EDA Tools: Questasim and ISE

Description: The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel0, channel1 and channel2. Responsibilities:

Architected the design

Implemented RTL using Verilog HDL.

Architected the class based verification environment using system Verilog

Verified the RTL model using System Verilog.

Generated functional and code coverage for the RTL verification sign-off

Synthesized the design

[2] SPI Controller Core - Verification

HVL: System Verilog

TB Methodology: UVM

EDA Tools: Questasim

Description: The SPI IP core provides serial communication capabilities with external device of variable length of transfer word. This core can be configured to connect with 32 slaves. Responsibilities:

Architected the class based verification environment in UVM

Verified the RTL module using System Verilog

Generated functional and code coverage for the RTL verification sign-off

[3] UART- IP Core – Verification

HVL : System Verilog

TB Methodology: UVM

EDA Tools: Questasim

Description: The UART IP core provides serial communication capabilities, which allow communication with modem or other external devices. UART will operate in three different modes – Simplex mode, Full Duplex mode and loopback mode. Responsibilities:

Architected the class based verification environment in UVM

Verified the RTL module using System Verilog

Generated functional and code coverage for the RTL verification sign-off

[4] GPIO – Verification

HVL : System Verilog

TB Methodology: UVM

EDA Tools: Questasim

Description: General purpose I/Os used in SoC

Responsibilities:

Architected the class based verification environment in UVM

Verified the RTL module using System Verilog. Generated functional and code coverage for the RTL verification sign-off

Post Graduation final project

Development of Compression Algorithms for Remotely Sensed SAR Data. Description:

Extracting the image from the SAR(Synthetic Aperture Radars) Raw Data, and compression of image on-board the satellite helps in reducing the memory required to store on-board and data is down-linked using lesser bandwidth.

Responsibilities:

Programming in MATLAB using image processing tool box and user friendly GUI (Graphical User Interface) and implemented compression algorithms efficiently. Post Graduation mini projects

1) Noise Elimination in EMG Signals using LMS Algorithm. 2) Novel Impulse Detector for filtering corrupted grey images. Description:

Finds application in examination of muscle tissues using Electromyography technique in medical applications. Removal of noise content from the grey images using image processing toolbox from Matlab.

Responsibilities:

Played the responsible role of programming in MATLAB taking into consideration the constraints imposed by the current techniques. Designed a framework for future enhancement of image processing.

Place : Bangalore Date: / /2015

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