RAMABHUPAL REDDY GOURI GARI

#**/*,****** ******,

Behind Arihanth Jewellery shop,

Kuvempu Main Road, acskoj@r.postjobfree.com

Hebbal-Kempapura, Mobile: +91-814*******.

Bangalore,India.

Career Objective:

Looking forward to associate myself with an organization, which has the potential for future growth and scope of learning, and further enhance my skills through constant learning and meet the challenges.

Summary of Qualifications

Good understanding of the ASIC and FPGA design flow

Expierence in writing C programming,C++,OOP Concepts

Experience in writing RTL models in Verilog HDL and

Test benches in SystemVerilog.

Very good knowledge in Verification methodologies(UVM).

Experience in using Industry Standard EDA tools for the front-end design and verification

VLSI Domain Skills

HDLs: Verilog

HVL: SystemVerilog

Verification Methodologies: Coverage Driven Verification Assertion Based Verification

TB Methodology: UVM

Scripting Languages: Shell script (make), Perl (Basics)

EDA Tool: Model sim, Questa and Xilinx ISE

Platform: Linux and Ubuntu

Domain: ASIC/FPGA Design Flow, Digital Design methodologies

Knowledge: RTL Coding, FSM based design, Simulation,

Code Coverage, Functional Coverage, Synthesis,

Static Timing Analysis, ABV

Protocols: AMBA AXI-3 &AXI-4,AHB,UART,GPIO

Professional Qualification

Certified Advanced VLSI Front Design & Verification Course

FromMaven Silicon Softech Pvt Ltd, Bangalore-Duration 6 months (AUG 2013-JAN 2014)

B.Tech (ETC2008-2013): Institution of Electronics and Telecommunication Engineers(IETE Bangalore)with an aggregate of6.37CGPA.

Intermediate (MPC 2006-2008): passed out from Board of Intermediate Education (Nagarjuna Junior College, Nandyal) with an aggregate of 84.4%.

S.S.C (2006): passed out from Board of Secondary School Education (St.josephschool, chagalamarri) with an aggregate of 81.1%.

Experience

Aug 2013 –Jan 2014, Maven Silicon, VLSI Front end Design and Verification Training Centre.

VLSI Projects::

GPIO IP CORE Protocol–Verification using SV and UVM

HVL: System Verilog

TB Methodology: UVM

EDA Tools: Modelsim, Questa -- Verification Platform

Key Features verified:

Number of GP I/O signals range from 1-32 and user selectable and can be bidirectional

All GP I/O signals programmed as inputs at hardware reset, can cause interrupts to the cpu

Extremely configurable, alternative input reference clock signal from external interface etc...

Architected the class based verification environment using system Verilog.

Generated functional coverage.

Router 1x3 – RTL design using Verilog HDL and Verification using SV and UVM

HDL: Verilog

HVL: SystemVerilog

TB Methodology: UVM

EDA Tools:Xilinx ISE, Questa 10.0b Verification Platform

Description:

The router accepts data packets on a single 8-bit port called data and routes the packets to one

of the three output channels, channel0, channel1 and channel2.

Features verified: Packet routing, Parity, Sending Packet, Timeout Check,Reading packet and etc...

Architected the design and described the functionality using Verilog HDL.

Architected the class based verification environment using system Verilog

Verified the RTL model using SystemVerilog.

Generated functional and code coverage for the RTL verification sign-off

Synthesized the design

AHB-APB Bridge: Verification using SV and UVM

Tools: Questa 10.0b

Features verified:

AHB pipelined operation with single bus master, single APB slave latched address and controls

Various Burst transfers such as unspecified lengths, incremental bursts, wrapping bursts

Non-sequential and sequential transfers for beat sizes byte, half word and word.

Project#: UART Verification (Course Project):

Architected the class based verification environment using system Verilog and UVM

Verified the RTL model using SystemVerilog.

Generated functional and code coverage for the RTL verification

Projects#:I have done some projects with my own interest to gain knowledge in Design

and Verification and also for my organization

1. Synchronous and Asynchronous FIFOs (Various Sizes)–Design &Verification.

2. Dual Port and Single RAMs (Various Sizes like 16KX8) –Design &Verification.

3. Washing machine controller –Design &Verification.

4. Simple Arbiter –Design &Verification and etc.

HDL: Verilog

HVL: SystemVerilog

TB Methodology: UVM

EDA Tools: Xilinx ISE, Questa 10.0b Verification Platform

Implemented all designs using Verilog HDL independently

Architected the class based verification environment using system Verilog and UVM

Verified the RTL module using System Verilog

Generated functional and code coverage for the RTL verification

AMBA AXI-4: Verification using UVM – Currently working

Tools used: Questa 10.0b

Features:

Supports unaligned data transfers using various byte strobes

Burst based transactions with only start address issued

Ability to issue multiple outstanding addresses and out of order transaction completion etc...

Academic Projects

Phase locked loop implementation with FPGA

Description:

A phase-locked loop (PLL) is an electronic circuit with a voltage- or current-driven oscillator that is constantly adjusted to match in phase (and thus lock on) the frequency of an input signal. In addition to stabilizing a particular communications channel (keeping it set to a particular frequency), a PLL can be used to generate a signal, modulate or demodulate a signal, reconstitute a signal with less noise, or multiply or divide a frequency. PLLs are frequently used in wireless communication, particularly where signals are carried using frequency modulation (FM) or phase modulation (PM). PLLs can also be used in amplitude modulation (AM). PLLs are more commonly used for digital data transmission, but can also be designed for analog information. Phase-locked loop devices are more commonly manufactured as integrated circuits (ICs) although discrete circuits are used for microwave.

Strengths:

Hard worker.

Analysing the things until there are clear to me.

Ability to quickly learn new concepts, applications.

Good time management skills.

Personal profile:

Name : Ramabhupal Reddy Gouri Gari

Father Name : Prathap Reddy Gouri Gari

Date of Birth : 10th May 1991.

Languages Known : English, Hindi, and Kannada&Telugu.

Permanent Address : H.sc.no 1-56, Singanapalle (Village), Owk (M),

Kurnool (DIST),

Andhra Pradesh,

India, 518196.

Declaration:

I hereby declare that the above written particulars are best of my knowledge and belief.

(Ramabhupal Reddy G)

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