JERRY A. MORRIS

*** ********* ******

Windsor, Colorado 80550

970-***-****

acskgr@r.postjobfree.com

SUMMARY

A detail-oriented Analog and Mixed Signal Integrated Circuit Layout Engineer, with demonstrated expertise in IC layout mask design. Skills include schedule estimating, CAD Directory setup, floor planning, power routing planning and design, pad-ring building, and block planning and building, with component matching, latch-up protection, top-level wiring, layer generation, verification, design reviews, PG (tape-out), mask ordering, documentation, and archiving. Established capabilities in troubleshooting, repair, cabling, shell scripting, component matching, trench isolation, ESD protection, and implementation of antenna repair. Leverages cutting-edge technologies to ensure corporate-wide process improvements, optimizing the profitability of initiatives. A pacesetter, who utilizes continuous improvement methodologies to ensure that infrastructure will support growth.

TECHNICAL SKILLS

Cadence Virtuoso, ASSURA, LVS, DRC, ERC Tools and Layout VXL, Calibre, Star-RC, Design Sync, ARC, CAPS, CAPSINFORMER, REDHAT, SUSSIE 11.0 Systems. Processes include, but are not limited to, CMOS9T5V (high voltage), CMOS9X (BiCMOS Scalable), CMOS7 (BiCMOS), ICB7, and LN14lpp(Global Foundries fin_FET at 14nm).

PC: Microsoft Office Suite, Cadence, Design Sync, Caps, Arc, Calibre, Star-RC

KEY ACCOMPLISHMENTS

As a Layout Engineer:

Supervised graphic design of integrated circuits from start to pattern generation or tape-out and ordered photo masks and writing supporting documentation.

Created directories, completed floor planning, read schematics, developed many different supporting blocks, built pad-rings with ESD structures, guard rings and latch-up protection, wiring and shielding, top-level adding generated layers, and process dependent manufacturing cells (cd cells, rev-letters, seal-rings, and nixies).

Performed running of LVS, DRC, and ERC antenna checks and density checks, and revised random XOR on all chips.

Conducted quality check, made stream file, and sent file for fracture by ordering photo masks and proceeding to write supporting documentation.

Developed directories, loaded schematics, floor planning, and power routing, and used Cadence Virtuoso layout editor, schematic editor, layout XL, LVS, DRC, ERC, and antenna and density checks. Hosted layout reviews and ordered masks.

Worked with and led teams on complex designs, using many different company processes.

Facilitated work on DACs, ADCs, Compairators, GSM base-station radio chips, base-station temperature sensors, two pin temperature sensors, general and precision temperature sensors, references and Bandgaps, built pad-rings with Merrill clamps and back-to-back diodes for ESD protection, and added manufacturing cells, including seal-rings, CD cells nixies, and corner anchors on larger chips.

Performed component matching, including cross-quad, inter-digitation, heat, process gradient and stress, and latch-up protection guard-rings and use of deepN isolation.

As a Digital Designer:

Utilized Timver software to check timing and modified VHDL code to fix timing.

Designed I/O cells, Oscillators, Drivers, Clock Trees, Drivers, and Rad-hard Latch.

EXPERIENCE

Cyient (Semtech) Windsor,Colorado

Senior Layout Designer 4 months 2015

Layout of 14nm finFet custom digital and integration of larger blocks, Level-shifters, bandgaps, pll, smaller cells, and modification of other blocks.

TEXAS INSTRUMENTS Fort Collins, Colorado

Layout Designer 2011-2015

Created physical layout of hundreds of designs from start to finish as sole Layout Engineer.

Created physical layout of trimable, precision temperature sensor with i2c buss and EEprom as sole Layout Engineer.

Created physical layout of two pin, precision temperature sensor with i2c buss and Seprom as sole Layout Engineer.

NATIONAL SEMICONDUCTOR CORPORATION Fort Collins, Colorado

Layout Designer 1994-2011

Created GSM base-station IC as part of a team effort.

Created self-calibrating SAR ADCs with matching switched capacitors, some on a team and some by myself.

Created DACs as part of a team effort to save time and shorten schedule.

COMLINEAR CORPORATION Fort Collins, Colorado

Layout Designer 1994

Created physical layout of current feedback op-amps of various performance criteria as sole Layout Engineer.

ADDITIONAL EXPERIENCE

TEXAS INSTRUMENTS, Dallas, Texas, Digital Designer, 1990-1994. Received architecture design as VHDL performed place and route with Synopsis, ran timing analysis and repaired VHDL. Added clock-trees, I/O and output Drivers. Designed and laid out Clock-Trees, I/Os, Drivers, and Oscillators. Developed radiation hard latch for DSP. Electronic Technician, 1972-1990. Supported manufacturing and field repair work. Transferred to IC design to support/test proto-type IC and support LASER maintenance.

EDUCATION

SOUTHERN METHODIST UNIVERSITY, Dallas Texas

B.S., Electrical Engineering, 1989

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