Drew Martin

212-***-****

acsifk@r.postjobfree.com

EDUCATION: University of Massachusetts Dartmouth North Dartmouth, MA BSEE

ASIC/FPGA TOOLS: DOORS, MKS, Cadence, Mentor, PCIe, PCI, SYSTEM VERILOG, VHDL, NCSIM, VERILOG-XL, TCL, SYNPLICITY Synplify, SYNOPSYS, LSI LOGIC, XILINX, ISE Foundation, Chipscope, DO-254, DOORS, MKS, Questa, ReqTracer, Matlab, Simulink, PYTHON, MAGMA, Vericov, Primtime, ATMEL, ACTEL, ALTERA, SOC, MODELSIM, SPW, DSP cores, TCP/IP, UNIX LINUX, C, C++

US PATENTS: Four separate patents for my design have been filed by Mitsubishi Electric Research Laboratories®.

6,426,749, 6,411,296, 6,356,265, 6,342,885

EMPLOYMENT HISTORY:

Parker Aerospace

Aug 2014 – Present

Irvine, CA Consulting FPGA verification engineer

Design and test of Lattice FPGA for flight control system for Gulfstream VII. FPGA RTL and testbench design in VHDL using Modelsim, Synplify, and Mentor Questa. Lab debug and validation of FPGA function and unit test. Avionics Motor control design and verification of control laws as applied per requirements. HRD and HRS Requirement conception, validation, and verification in accordance with DO-254 process assurance. Extensive use of DOORs and MKS for document control and requirement traceability. Successfully discovered and corrected multiple asynchronous anomalous behaviors in FPGA design and implementation. Streamlined VHDL code and applied more detailed constraints to effectively meet timing and area constraints during synthesis and place and route.

Curtiss Wright

Jun 2013 – Feb 2014

City of Industry, CA Consulting FPGA Design Engineer

Verilog Design and test of multiple Xilinx FPGAs. Use of Modelsim to simulate and set up testbench environment. Utilized Xilinx PlanAhead to synthesize, and place and route FPGAs. Design and test of FPGAS used as Discrete Input/Output processing functions for a Data Concentrator.

Heavily involved with DO-254 HRD, HRS, and HSI development. Defined requirements and derived requirements as well as traceabilty in accordance with DO-254 process assurance. Maintained and updated documentation in DOORS.

Northrup Grumman

Aug 2012 – Feb -2013

Arlington Heights, IL Consulting FPGA Design Engineer

VHDL Design and test of Xilinx Virtex II FPGA. Use of Mentor Questa, Synopsys Synplify, Xilinx ISE and PlanAhead tools to simulate, synthesize, and place and route FPGAs. Design and test of PCI and gigabit Ethernet MAC PHY cores. Lab debug using Chipscope and break-out test fixture. Defined and updated design and test requirements.

Parker Aerospace

Sep 2010 – Jun 2012

Elyria, OH & Irvine, CA Consulting FPGA verification engineer

Test verification and validation FPGA based electronics of center tank fuel pump for Airbus A350,. Creation, validation, and verification of test procedures written in VHDL and System Verilog in accordance with DO-254 standards using Modelsim, Mentor Graphics Questa, and ReqTracer. Incorporation of test procedures and results into Hardware Verification Plan (HVP) based upon requirements from PHAC, HDD, HRD and other documents. Actively participated in requirement generation and validation via DO-254 standard. Lab debug of FPGA based control board electronics . Incorporated the use of ReqTracer to improve coverage of requirements traceability in all aspects of documentation and design.

Medtronic/Phiso Control

Jan 2008 – Dec 2009

Redmond, WA Consulting FPGADesign Engineer

Led FPGA redesign and verification effort for new cardiac defibrillator. Verilog RTL coding and testbench generation. Sequential state machine design of FPGA which interfaces between a SBC and existing ASIC. Xilinx Virtex 5 development including implementation and validation of DSP core. Implementation of PCIe core and interface logic. Multiple clock and reset asynchronous design needed elaborate timing and clock definition constraints. Design was compiled and placed and routed on an Actel part using Synplicity Synplify and Modelsim 6.3f. FPGA debug using Chipscope. Lab debug using Synplicity Identify.

NXP

Sept 2007 – Nov 2007

San Jose, CA Consulting ASIC Verification Engineer

Led back-end effort for video input processing 65nm process CMOS ASIC. Developed design constraint scripts using TCL and successfully met all timing, floorplanning, and power constraints by performing DRC. Developed test cases for, H.264, MPEG2/3, MPEG 4, as well as standard video streaming formats (NTSC and PAL)for both. RTL compilation and simulation using Cadence ncsim. Verification of windowing, scaling, dithering functions of embedded SOC IP core. Developed and integrated SOC with PCI and I2C interface. Sucessfully verifed DDR memory thoughput and integrity of up to eight multiplexed and programmable video data streams.

MOOG

Aug 2006 – Aug 2007

Salt Lake City, UT Consulting FPGA Verification Engineer

Performed FAA compliance Verification of Xilinx Virtex 2 FPGA using VHDL for electro-hydraulic actuator interface to main flight computer for the Boeing 787 dreamliner, Gulfstream IV and Bombardier Challenger jets. Verified FPGA function using Modelsim and VHDL. Designed testbenches to check compliance based upon specification requirements derived from DO-254. Successfully designed test verification suite that effectively simulates and verifies function of CRC Manchester encoded serial data bus. Performed functional verification on static post-route timing analysis of Atmel FPGA on ARINC-429 CCA and flight control avionics.

Peerless

Dec 2005 – Mar 2006

El Segundo, CA Consulting FPGA Design/Verification Engineer

Verilog design of 4 channel print imaging processor CMOS ASIC for multifunction printer. This video processor generated variable line and frame syncs for print and overlay print image processing. Design of high-speed memory access control DMA controller interface, state machine logic, and testbench design using Cadence ncsim, Verilog XL and VCS. Updated and designed system and block verification scripts written in Verilog. Wrote synthesis scripts for Synopsys DC shell and Synopsys Primetime to verify design met area and timing constraints. Development of ASIC design flow for next generation SOC (System on Chip) design.

BAE Systems

May 2005 – Aug 2005

Lexington, MA Consulting FPGA Design Engineer

Verilog design of video pipeline processor for Xilinx Virtex 2 FPGA to be used in infrared camera. Design included a range of mathematical functions base upon image processing algorithms to correctly display temperature on LCD display in both PAL and NTSC format. Design of System timing generator and AMD Au1100 processor interface logic with PCI. Used Modelsim as an environment for testbench generation in verilog for verification of functional blocks. Job also included verification of mixed signal logic in SOC application integrated with Xilinx FPGA for targeted for an ASIC for a weather imaging mapping satellite.

Telephonics

Sep 2004 – Dec 2004

Farmingdale, NY Consulting FPGA Design Engineer

VHDL design on RS-485 interface in communications system including codec interface design to various proprietary serial buses. Xilinx design of FPGA using Spartan and Virtex libraries. Synthesis and timing verification using Synplicity Synplify, Simulation using Aldec simulator. Functional verification of audio router Xilinx FPGA using ISE Foundation in VHDL.

SMSC

Sep 2003 – Aug 2004

Happaugue, NY Consulting ASIC Design Engineer

Verilog design of Flash ROM access controller for 8051 based microcontroller 180nm ASIC. Used Synopsys for synthesis of this block. Ran both new and legacy based tests using NC Verilog functional verification as well as VCS on various modules of within this ASIC. Debug of mixed-mode ASIC design using Debussy/Verdi.

CYMER

Jun 2002 – Oct 2002 Cymer, Inc.

Cambridge, MA Consulting FPGA Design Engineer

Design of Timing and Laser Firing Control Module for dual-chambered excimer laser. The first Xilinx Virtex II FPGA board design required measurement resolution timing to 250ps. This Verilog design also incorporated a RS-422/RS-485 interface and 16-bit CRC function. The second FPGA required VHDL design using Modelsim and integration of another fire control module which produced laser timing signals.

ONEX

Jan 2000 – May 2001

Bedford, MA Consulting ASIC Design Engineer

Design of Datalink Manager for ATM and TCP/IP router processor. This design (2 million + cells) was part of an 8 million cell ASIC designed in verilog using IBM SA27E CMOS technology. Design consisted of various caching and queuing schemes based upon PHY and QOS to be performed by and ATM/TDM/IP routing switch and processor chipset. ATM, MPLS, SONET/SDH, packet processing and data transfers were performed in virtual real-time. Verilog design completed using VCS, Verilog XL.

Mitsubishi Research

Sep 97 - Nov 98 (MERL)

Cambridge, MA Consulting ASIC Design Engineer

Verilog design and verification of main component of 2 million gate CMOS ASIC using the new IBM 5SE 0.35um and IBM SA-12E 0.25. Conception, design, and test of 3-D volume graphics ASIC. Design of the reflectance map shader based upon the Phong Shading algorithm. High speed memory design and memory interface. Hardware design digital filtering.

Inframetrics

Jul 96 - Jul 97

N. Billerica, MA Consulting FPGA Design Engineer

Redesign of infrared camera controller design using Xilinx 4013 FPGA. Digital Design and test of FPGA design written in VHDL. Responsible for RTL design continuity and system update of video control FPGA. System integration and board level test of PAL and NTSC format video from infrared front end data.

Qualis

Jun 96 and Sep 96 Verilog Instructor (Qualis Design Corp)

Ottawa, ON Canada - Portland, OR

Taught Verilog Course for Electrical Engineers in conjunction with Qualis Design Corp and various offsite locations. Course incorporates lectures and labs including Verilog Coding convention, Verilog for synthesis, Verification using Verilog, and Verilog Testbench Generation.

Tait Electronics

Sep 95 – Apr 96 Tait Electronics Ltd.

Christchurch, New Zealand ASIC Design Consultant

Design and implementation of Xilinx XC4000 series FPGA used in mobile communications product. Optimization and synthesis of synchronous/asynchronous logic written in VHDL using Synopsys. Confronted and successfully overcame load, timing and area concerns while completely optimizing circuit performance based upon specification.

Intel

May 94 – Oct 94

Hillsboro, Oregon Consulting ASIC Design Engineer

Optimization and synthesis of synchronous/asynchronous logic ASIC design in VHDL using Synopsys and LSI Logic Core functions for integration. Ensured that ASICs met all design and test criteria and before final tape-out. Also In charge of optimization and synthesis of synchronous/asynchronous logic using Synopsys targeted for Toshiba library. Confronted and successfully overcame load, timing, and area concerns using Synopsys design compiler and TCL scripts.

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