SHRUTHI AB Mobile: +91-814*******

M.Tech(VLSI) +91-990*******

Mahalakshmi Layout Email: acs53l@r.postjobfree.com

Bangalore 560086,Karnataka-577201.

Objective

Seeking a lecturer position with a good Education society where I can contribute my skills for success and synchronize with new technology knowledge while being resourceful, innovative and flexible.

Technical skillsc

EDA Tool :FPGA, ALTERA Quastus – II

Hardware Description Language :VHDL,Verilog,System Verilog.

Simulator :Model Sim,Spice.

Cadence tool suite :Virtuoso Schematic Editor, Virtuoso.

Layout Editor,SOC Encounter, NC-Verilog.

Synopsis Tool Suite :Design Compiler,Design Analyzer.

Software skills :C,Cpp.

Platforms :Linux, Windows.

Architecture :µP 8085,86

Assembly Programming µP 8085,86

Hardware Expertise :Altera FPGA Board (Processor Based

System Design)

TB Methodology :UVM basics

Bus Protocol :AMBA AXI,AHB,APB,SPI.

Technical Expertise

ASIC Flow Complete Frontend and Back end Flow Clock Tree Synthesis, Signal Integrity, Static Timing Analysis,SDC,ASIC/SOC Verification analysis under UUT, Verilog functional coverage, OVM/UVM Verification basics knowledge, system verilog basics,Scripting Languages, Verification and Testing, Digital IC Design, FPGA Based System Design, Low Power CMOS VLSI Design, IC Technology, Analog Circuit Design, ASIC & FPGA Flow, Analog & Digital Communication, Digital Logic Design.

Education

M.Tech in VLSI Design and Embedded System 2015:

VTU Extension Centre, UTL Technologies Ltd., Visvesvaraya technological University. (73%)

Industrial/ Academic Training

•Training on Cadence RTL Compiler – VTU Extension centre, UTL Technologies Ltd.

•Training on Cadence Virtuoso – VTU Extension centre, UTL Technologies Ltd.

•Training on System Verilog- VTU Extension centre, UTL Technologies Ltd.

•Training on Linux Operating System-VTU Extension centre, UTL Technologies Ltd

Conference/workshops

• Attended workshop on Verification IP organized by Ellite-plus coffee club bangalore.

•Attended seminar on Micro-Nano Technology organized by IISC, Bangalore.

•Attended seminar on VLSI technology trends organized by UTL technologies Ltd.

•Attended seminar on Multi frequency Multi functional Electrical Impedance.

Course project :

M.Tech

1. Project Title :Design And Implementation of Keyboard interface on FPGA .

Platform:Quastus- II

The design a system that provides an interface between Spartan-3 starter kit board and a PS2 style keyboard.our system will display the scan code sequence, generated by the keyboard when each key is pressed.

Task involved : Analysis of the code coverage and functional coverage and the design is created using VHDL.Codecoverage analysis of keyboard interface using verification environment.

2.Project Title :Design and Verification Analysis of AMBA APB Protocol .

Platform: Coding (Verilog HDL),Simulation(NC Launch) & Synthesis (RTL Compiler).The SoC (System on Chip) uses AMBA (Advanced Microcontroller Bus Architecture) as an on chip bus. APB (Advanced Peripheral Bus) is one of the components of the AMBA bus architecture. APB is low bandwidth and low performance bus used to connect the peripherals like UART, Keypad, Timer and other peripheral devices to the bus architecture. This work gives the AMBA APB bus architecture design.

Task involved: The design is created using the verilog HDL and is tested by a verilog testbench. This design gives the verified result by using UVM (Universal Verification Methodology)

3. Project Title : Timing Verification of digital designs.

Technology evolution has added lot of functionalities in to chip to improve the performance. In the design data is frequently transferred from one clock domain to another may lead to timing violation due to clock domain crossing hence timing verification have become a major challenge in present SOC.

Task involved: Capturing the timing constraints in SDC and analyzing the timing paths for any violation in digital designs.

My Strengths

Hard working, creativity and Confidence

Declaration

I declare that all above information furnished in this application true to best of my Knowledge and belief.

Place: Bangalore Regards date: (shruthi)

Contact this candidate