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Electrical Engineering Design

Location:
San Jose, CA
Posted:
October 06, 2015

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Resume:

KRISHNABAHEN DOBARIA

**** *** *******, *** #***, San Jose, CA-95126

703-***-****

Email: acry9v@r.postjobfree.com

LinkedIn: http://www.linkedin.com/in/krishnadobaria/ Objective Seeking a full-time position in the field of Electrical Engineering. Education Master of Science, Electrical Engineering Expected-12/15 San Jose State University, San Jose, CA GPA- 3.50/4.00 Bachelors of Engineering, Electronics and Communication Engineering 07/09-06/13 Babaria Institute of Technology, Vadodara, Gujarat, India. CGPA-8.58/10 Graduate ASIC CMOS design Digital System Design and Synthesis Coursework SoC Design Digital Design for DSP/Communication using FPGA High Speed CMOS Circuits Computer Architecture

Linear System Theory Semiconductor devices

Skills Programming Languages: Verilog, System Verilog, VHDL, Perl, C Language, C++ Language, Visual Basic Instruments: Oscilloscope, Signal Generator

Other Tools: Cadence design tools, Synopsys VCS, NC Verilog, Altera Quartus II,Altera Modelsim, Keil uVision,PSpice, RS Linx, Intouch Wonderware, Xilinx ISE, Matlab

Projects Spread Spectrum Search Engine (Tool : Synopsys VCS) 10/14-12/14

It is designed in Verilog to find phase and frequency of direct sequence PSK spread spectrum signal mixed with several other SS signals below noise floor.

It has 32 bit DDS sine frequency generator and PRN generator to generate reference signal and uses 32 correlators to compare the input signal with it from 60MHZ to 300MHz. 8-bit Scalar Processor (Tool : Synopsys VCS) 09/14-12/14

It is a simple design of 8 bit processor in Verilog. It executes simple instructions like JMP, CMP, RDM etc., as well as the basic operation of processor using interfaces.

All machine codes are 8 bit and memory is designed in the testbench. Hardware Implementation of Tree Detection For Autonomous Vehicle (Tool: Altera Quartus II) 01/15(Current project)

Doing this project under the guidance of Prof. Chang Choo.

It uses Texture based Segmentation using series of Gabor filters at different orientations to recognize the unique texture of trees on road for real-time application.

Initial Algorithm has been tested on MATLAB 2015 and Hardware is implemented using Altera FPGA DE-1 board. Designing of Bus Arbiter with 6 masters and 9 slaves. (Tool: Synopsys VCS) 02/15-05/15

It is designed in System Verilog for arbitration of bus which communicates between 6 masters and 9 slaves with each master having different amount of cycle usage at frequency of 100MHz.

Priority technique is used for arbitration of 6 master and 9 slaves. 5 Stage Pipelined MIPS CPU (Tool: Synopsys VCS) 04/15-05/15

Design includes simple 8 instructions like ADDI, SW, LW etc. with 256 bytes of memory and pipelined MIPS Architecture.

Design is implemented in Verilog Language and all instructions are 4 bytes of size.

A simple program of adding 100 numbers is implemented to test the instructions without considering any Hazards. 16 Point FFT Design (Tool : Altera Quartus II ) 03/15-05/15

16 point butterfly design is implemented using Altera Mega wizard modules bfproc (4 point butterfly) and cmult

(complex multiplication) instantiation in the main design with 4 bit inputs and outputs.

It is designed using Verilog and successfully synthesized in Altera Quartus II 13.0sp1.

Hardware is implemented using Altera DE-2 board using Qsys and Megawizard Software build tools for Eclipse by making Hardware Accelerator of 16 point FFT.

Radix-8 Montgomery Multiplier for 32 bit word (Tool : Cadence Virtuoso) 02/14-05/14

It multiplies two large number using bit shifting and addition operations easily using Cadence tool.

It works on high speed and low power.

The entire circuit is built in Pseudo NMOS logic. Industrial POSITRONICS PVT. LTD. Vadodara, India. 06/12-05/13 Training Project Title: Automation And Controlling of Conference Hall Using PLC (Tool : RS Linx )

Automating different elements present in conference hall such as door system, AC’s, Fan’s, brightness control of light, projector and wireless access of these devices using GSM module and DTMF circuit to provide security against theft. SOFCON INDIA PVT. LTD. Vadodara, India. 05/12-06/12

Automation Training of PLC and SCADA..



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