V.BHAVYA

*-**, ********** *****,

AKKARAMPALLI ROAD, TIRUPATI,

517501 .

MOBILE NO: +91-999*******

LAND LINE NO: 087*-*******

email: acry6m@r.postjobfree.com

OBJECTIVE

I aspire to excel in my profession and contribute towards the growth of a multi-functional organization resulting increase in profits of the stake holders both as an organization as an individual.

EDUCATIONAL QUALIFICATION

COURSE

UNIVERSITY/BOARD

SPECIALIZATION

INSTITUTE/UNIVERSITY

YEAR OF PASSING

PERCENTAGE

M.TECH

VIT University

VLSI

VITUNIVERSITY

2014-2016

7.6(CGPA)

(Sem -1)

B.TECH

JNTU ANATAPUR

ECE

SREE RAMA ENGINEERING COLLEGE,TIRUPATI

2010-2014

79.5%

INTERMEDIATE

BOARD OF INTERMEDIATE

MPC

ROYAL VICTORY

JUNIOR COLLEGE,TIRUPATI

2008-2010

82.7%

S.S.C

BOARD OF SECONDARY EDUCATION

SRI VENKATESHWARA CHILDRENS HIGH SCHOOL, TIRUPATI.

2007-2008

82.66%

Computer Skill Set

Languages : C programming, Verilog HDL, PERL Script, TCL script, VHDL

Electronic Packages : SOC encounter, Cadence NC launch, Cadence Virtuoso, Altera (Quartus II), Model SIM

PROFESSIONAL EXPERIENCE:

IN-plant training at Prasar bharathi June 2012 on F.M Transmitter (AIR-Tirupati).

ACAMEDIC INTEREST

Digital IC Design, low power icdesign,ASIC design,Physical design,SOC design.

ACHIEVEMENTS

Secured in third prize in the”national level technical symposium for the project “Foot step Based power generation”.

PUBLICATIONS

Project paper” Design and performance analysis of reversible logic based ALU” published in SCOPUS Journal(2015)

PROJECT LIST

Performance Analysis of the Multiple Sense Amplifier for 6T SRAM, Second Semester M.TECH project, 2015: This project involves the different kinds of sense amplifiers for 6T SRAM application. The proposed design is implemented in 90nm technology using cadence virtuoso.

ASIC Implementation of IS-95 Forward channels CDMA, Second semester M.TECH, 2015: This project involves the ASIC implementation of IS 95 Forward Channel CDMA. The simulation & synthesis done in 180nm technology through Cadence NC launch. Physical design is accomplished with SOC Encounter.

Design and performance analysis of reversible logic based ALU, First Semester, MTECH, 2014: This paper involves the designing Arithmetic and Logical Unit (ALU) using reversible gates which helps to reduce the power consumption and also to increase the speed.

Design & Implementation of low cost & power FIR Filters, First semester, M.TECH, 2014: This project proposes the improved truncated multiplier and modified radix 4 booth multiplier and also optimization of bit width and hardware resource. The proposed design accomplished in FPGA Platform.

VLSI based Robust Router Architecture B.TECH, 2014: This project deals with implementation of VLSI robust router architecture for networking problems, through which reduction in the latency issues& maximize the speed through switching protocols.

PERSONAL SKILLS

Demonstrated leadership qualities.

Ability to deal with people diplomatically.

Willingness to learn team facilitator hard work.

PERSONAL PROFILE

Name : V.Bhavya

Father’s Name : V.Subramanyam

Nationality : Indian

Date of birth : 07-06-1993

Languages known : English, Hindi

DECLARATION: I hereby declare that above furnished information is true to the best of my knowledge.

Signature

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