KOUSHIK RAMAKRISHNAN

*** *. *** ******** **. San Jose, CA 95112

Mobile: 312-***-**** Email: acry3l@r.postjobfree.com

O B J E C T I V E

Seeking a full time position in the field of Hardware verification/testing where I can utilize my skills, knowledge and experience.

TECHNICAL PROFICIENCY

PRE-LAYOUT SIMULATOR

Questa-Sim, NC-Sim, Altera Quartus 2, Model-Sim

LANGUAGES & METHODOLOGIES

Verilog, System Verilog, UVM, UVM_RAL, C, C++,

Perl, Shell scripting/C-shell

BUS PROTOCOLS

I2C, AMBA-AXI, UART, USB TYPE-C

OPERATING SYSTEMS

Windows, Unix, Linux

LAYOUT EDITOR

Cadence Virtuoso

OTHER TOOLS

Cadence Sim-Vision, Atlanta ATPG, LT-Spice, P-Spice, MATLAB

SUMMARY OF SKILLS

Specialization in ASIC Design and Verification, Scripting in Perl, and Programming in C/C++.

Familiarity with Logic design, Linear and constrained-random test-bench architectures, OOPS concepts, Assertion-based verification, and Functional coverage.

Experienced in programming with Verilog, System Verilog, and SV-UVM.

Familiarity with MIPS ISA, Branch Prediction, Cache replacement schemes, Memory hierarchy, and Cache coherency.

WORK EXPERIENCE

ASIC VERIFICATION ENGINEER - NXP SEMICONDUCTORS (VIA VERIFAST TECHNOLOGIES)

USB TYPE-C

(August 2015 – Present)

Currently developing Register Abstraction Layer (RAL) tests for register verification in UVM.

I2C SERIAL BUS

(February 2015 – July 2015)

Developed and integrated UVM RAL model for registers working on I2C protocol.

Wrote and implemented RAL tests, including Register Reset (POR) and Bit-Bash, for multiple register banks using virtual sequences.

AMBA AXI-LITE UVC

(December 2014 – January 2015)

Developed functionality for the components – Master Driver, Monitor, and Scoreboard in UVM.

Implemented Master sequences and virtual sequences with sequence-item retry functionality which could be controlled from the test.

Implemented System Verilog Assertions, Functional Coverage for protocol and signal checks, and regressions using Makefile.

UART Controller

(August 2014 – November 2014)

Developed verification environment for UART controller in System Verilog and UVM.

Designed a Serial to Parallel converter for UART with an Asynchronous FIFO using Verilog HDL.

Developed C-shell and Perl scripts for automated test generation, accepting and displaying arguments, and comparing values/strings.

ACADEMIC PROJECTS

LOGIC DESIGN

Designed a 16-bit Kogge-Stone adder and a 16-bit Wallace-tree adder in Verilog HDL and simulated in Altera Quartus2.0 and achieved propagation delays of 16ns and 19ns respectively.

Designed a 2*2 switch using a synchronous FIFO in Verilog HDL and simulated in Model-Sim.

VLSI TESTING & RELIABILITY

Developed compression algorithms in C++ to perform Huffman and Arithmetic encoding (for BIST) to reduce test data volume in comparison with Atlanta ATPG compressed test vectors and achieved a relative compression of 90%.

COMPUTER ARCHITECTURE

Performed compiler optimizations to improve the performance of Dense matrix multiplication (N*N array size) using various blocking methods.

Implemented MRU (Most Recently Used) cache replacement policy in C language and compared its performance to other replacement policies like Random, LRU and FIFO.

PARALLEL PROCESSING

Performed LU decomposition on a matrix and found its determinant using MPI-C on a mesh.

Implemented matrix multiplication using Cannon's algorithm on an array of data (up to 100000 elements) distributed in blocks across 16 nodes using MPI-C program.

Implemented Find Maximum MPI-C program on an array of integer data by distributing it across all nodes in ring and hyper-cube topology.

EDUCATION

University of Illinois, Chicago, Fall-2012- Spring-2014

Masters of Science, Electrical and Computer Engineering GPA - 3.5/4.0

Vel Tech Engineering, Anna University, Chennai, India, 2008-2012

B.E (Bachelor of Engineering) Electrical and Electronics Department GPA - 8.0/10

RELATED COURSEWORK

Introduction to VLSI

Advanced VLSI

Analog and Mixed Signal VLSI

Digital Signal Design

Digital Design using CAD

Testing and Reliability of Digital Systems

Computer Architecture

Parallel processing

High performance Processors and Systems

OTHER WORK EXPERIENCE

GRADUATE ASSISTANT - UNIVERSITY OF ILLINOIS, CHICAGO- (April 2013- February 2014)

Maintained the college network through Active Directory for 200+ internal users & workstations.

Functions included HW/SW trouble-shooting, Network Administrator, and other IT services.

Conducted presentations for staffs towards usage of various technologies like SSH shell, Remote Desktop, application servers in both Windows and Linux platforms.

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