ARTI PATHAK

+919*********

acrvjn@r.postjobfree.com

Objective

“To work in a organization where I can use my skills to achieve the organization objective and get conductive environment to Learn and grow.”

Education

Passing year College Percentage Course

2013-2015 CDAC Noida 84.36% M.Tech (VLSI Design)

2012 CDAC Noida 71% Diploma (Embedded system & Design) 2007-11 PSIT, Kanpur 80.02% B. Tech (EC)

2007 JDSVM, Kanpur 85.17% Class XII (CBSE Board)

2005 JDSVM, Kanpur 78.83% Class X (CBSE Board)

Technical Skills

C Language, Shell scripting (UNIX)

Verilog (Hardware Description Language)

AVR Microcontroller, ARM Processor

FPGA Spartan 3E

Schematic designing And Analysis (Mentor Graphics)

Others: knowledge of the Microsoft office and expert in Excel and PowerPoint

Operating systems: Windows XP, Vista, 7 and Linux

EDA Tool Used : X-Manager(Mentor Graphics IC Station Pyxis), ModelSim, ISE Design Suit Area of Interest

Verilog(HDL),Schematic Designing and Analysis, Embedded System, Digital Electronics. Industrial Training

Four week summer training from AIR (All India Radio) Station, Kanpur in 2009. I tried to achieve full knowledge which I could, in best possible way out there. Focused on different types of transmission and reception techniques & systems and the related technology regarding Electronics and Communication Field.

Four week summer training from HAL (Hindustan Aeronautics Limited), Kanpur in 2010. I tried to achieve full knowledge which I could, in best possible way out there. Focused on different systems used in Aircraft and related technologies regarding to Electronics and Communication field. Projects

Self Parking Car : The objective of this project is to make microcontroller based model which is based on the parking problems in limited space where parking a car is vital skill. This project will help to park your car successfully in a limited space automatically.

Automatic Room Lightening with Visitor Counter: The objective of this project is to make a controller based model to count number of persons visiting particular room and accordingly light up the room.

Modelling RAM in Spartan3E FPGA: The objective of this project is to model the Distributed RAM as Shift register and Block RAM as FIFO.

Design & Analysis Of Topologically Compressed Low Power Flip Flop With Its Application: The objective of this project is power reduction without any degradation of timing performance and cell area in master slave D flip flop

Achievements

Awarded for Excellence Academic Performance in B.Tech 1st year at college in 2008.

Awarded for Excellence Academic Performance in B.Tech 2nd year at college in 2009.

Awarded for Excellence Academic Performance in Sanskrit subject for 97% marks in 10+2 standard at school in 2007.

Awarded for Academic Excellence Performance in Information Technology subject for 95% marks in 10 standard at school in 2005.

Personal Details

NAME: Arti Pathak

DOB: 6th july 1990

Father’s Name: Arun Kumar

Mother’s Name: Usha Pathak

Nationality: Indian

Permanent address: 117/ ‘O’/245-A Geeta Nagar, Kanpur Contact No.: +919*********, +919*********

Language Known: English, Hindi

Declaration

I hereby declare that the above-mentioned information is correct up to my knowledge and I bear the responsibility for the correctness of the above-mentioned particulars. Place: Noida Arti Pathak

Date:

Contact this candidate