LINXI HAN

*** * ******* ** *** *** acrtmu@r.postjobfree.com Tempe, Arizona, 85281 480-***-****

SUMMARY

Two years of strong academic experience in design, analysis and synthesis of digital circuits using Cadence, Verilog/System Verilog, HSpice and ModelSim. Expertise in static timing analysis (STA), components design and Register Transfer Level (RTL) development. Seeking for a full time position as an ASIC designer.

EDUCATION

Arizona State University, Tempe, AZ

M.S., Electrical Engineering

GPA: 4.0/4.0 May 2015

Huazhong University of Science and Technology, Wuhan, China

B.S., Optoelectronic Information Engineering

GPA: 3.6/4.0 June 2014

PROJECT EXPERIENCE

32-bit Multiplier Design, ASU

November 2014

Realized the function of a 32-bit multiplier with Verilog code, sped up the multiplication by booth encoding, Wallace tree, [4:2] and [3:2] compressors

Minimized the total area by increasing core utilization to get better floorplan and adjusting the width and spacing of power strips

Optimized the pipelining to achieve smaller power and larger throughput, got a decent quality metric measured by (Total latency)2 Power Area

Passed the DRC and LVS rules and completed the primetime measurement that only 10% students succeeded

Register File Design, ASU

October 2014

Designed a 16 entry 16 bits wide dynamic register file (RF) with one read port and one write port

Arrayed the transistors moderately to reduce the area of a single register file

Found methods to improve the speed and energy, such as magnifying the dimension of two pull down transistors

Obtained better performance of energy-delay products by way of detecting the fastest frequency

Full Adder Design, ASU

April 2014

Devised a one-bit full adder. Created the schematic with 28T adder and five dynamic TSPC registers to acquire smaller delay

Brought about the compact layout to narrow the total area and avoided laying much highly resistant poly

Minimized the average energy-delay product by correctly sizing the transistors

Additionally planned a 16-bit full adder with layout

PVT Variations of FinFETs, ASU

April 2015

Investigated the influences of fabrication process inaccuracies, mutative power supply voltage and operating temperature on FinFETs.

Made efforts to enhance the reliability of FinFETs, for instance, stacked the transistors and selected lower supply voltage to decrease the leakage current, maintained the temperature at around 20 degree for the purpose of both less delay and leakage

ACADEMIC PERFORMANCE

Obtained the fundamental concepts and experimental experience in static CMOS and delay, logic efforts, sequential circuits timing, on chip interconnects and power supply distribution through VLSI course. Considerably understood CMOS short channel effects, aging effects, PVT variations and structure of FinFETs according to VLSI reliability course.

WORK EXPERIENCE

Chinese Students and Scholars Association, ASU

October 2013 – May 2014

Chinese 2014 spring festival evening event planner and organizer

Communicated with the school administration, applied for activity fee and sponsorship

Planned and organized multiple school events

Huagong Technology, China

June 2013 – August 2013

Technician in the Production line

Helped to make the switching mode power supply with DC converter, MOSFET and transformer

Welded PCB and installed the separated elements into an integral power box

AWARDS

Excellent Student Leader Scholarship, Huazhong University of Science and Technology

Fall 2010 and Fall 2011

SKILLS

Computer Skills: Cadence, HSpice, ModelSim, Matlab, Verilog, C, Java, Python

Language Skills: Native in Chinese, professional working proficiency in English

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