KERRY L GOODWIN

**** ********** ** **** ********* Pa (C) 267-***-**** (H) 215-***-**** (E) acrsuu@r.postjobfree.com Linkedin Profile: https://www.linkedin.com/pub/kerry-goodwin/44/32b/1b5 PROFILE

More than 28 years of experience photomask layout, reticle layout, IV testers, litho marks, fiducials and fracturing data with bops and comps. The goal is to maximize yields on wafer while making opportunities to improve the quality and efficiency of the wafer and process.

Experienced in developing and analyzing the mask process to improve the photomasks, reduce errors and promote quick turn from design to photomask (Tape- out).

PROFESSIONAL EXPERIENCE

TAPEOUT COORIDNATOR/MANGER

AVAGO TECHNOLOGIES, ALLENTOWN, PA

2014 - 2015

Functioned as a Project Manager to coordinate people, process and data required for photomask tape-out.

Managed and Documented timelines, milestones and executables for the tape- out process

Functioned as a Reticle Layout Engineer for dedicated Reticle Set and MPW

(Multi Project Wafers)

Documented and Coordinated IV structures

Managed Fabrications Specifications

Created Purchase Orders Photo Mask and Bump Mask

Designed superblocks, merge multiply GDS (Graphic Data System) databases in to one database for mask tones functionality and reduce turnaround time (TAT).

Negotiated photomask pricing with photomask vendor.

Documented and Coordinate required bump GDS and mask specs for multiply bump vendors

Managed all IV structures and fiducials libraries.

Designed and Maintained product tape-out webpage

Created and Maintained BOMs (Bill of Materials) for IC design and manufacturing MPW/RETICLE/TAPEOUT ENGINEER

LSI CORPORATION, ALLENTOWN,PA

2007-2014

Functioned as an Reticle Layout Engineer for dedicated and MPW (Multi Project Wafers)

Documented and Coordinated IV structures

Managed Fabrications Specifications

Created the Purchase Orders for Photo Mask and Bump Mask

Designed superblocks, merge multiply GDS databases in to one database for mask tones functionality and reduce turn time.

Generate required bump GDS and documentation for bump vendors.

Managed all IV structures and fiducials libraries.

Created and Maintained BOMs (Bill of Materials) for IC design and manufacturing EDUCATION

Associates Degree in

Electronic Engineering

Lincoln Tech

July 1987

Graduated top 2%

Microelectronic Fabrication

Technology, Lehigh

University

Certifications

Cadence CAD Program

Mentor Graphics CAD

program

AREAS OF EXPERTISE

Build Partnerships

Create a Climate for

Success

Job Knowledge/Technical

Skills

Learn Continuously

Seizes Opportunities for

improvements

Thinks Strategically

Transform Strategy into

Results

PROFESSIONAL SKILLS

SAP

Oracle

Agile

GRED graphic editor

Cadence

Calibre

WEBEX

UNIX

Excel

Word

Outlook

PowerPoint

Access

Cats Fracturing

KERRY L GOODWIN

1070 Kraussdale Rd East Greenvile Pa (C) 267-***-**** (H) 215-***-**** (E) acrsuu@r.postjobfree.com Linkedin Profile: https://www.linkedin.com/pub/kerry-goodwin/44/32b/1b5 MPW/RETICLE/TAPEOUT ENGINEER

AGERE SYSTEMS ALLENTOWN, PA

2000 - 2007

Wrote UNIX scripts to reduce turnaround time and manual errors.

Documented tape-out specs for multiply external manufacturing vendors for IC.

Documented processes and procedures for ISO 9000

Functioned as a Reticle Layout Engineer for dedicated and MPW (Multi Project Wafers)

Documented & Coordinated the IV structures

Managed Fabrications Specifications

Managed and Constructed the Superblock

Improved the turnaround time(TAT) by 75 % for each superblock construction ARRAY/RETICLE/FRACTURE ENGINEER

AT&T, ALLENTOWN, PA

1987-1996

Documented specifications for IC’s

Functioned as a Job Deck Planner and Frame/Wafer Engineer to create frames with IV testers/litho marks, reticle layout and job decks for AT&T, OEM and Non-AT&T customers

Managed stringer fixes on existing data to remove floating metal features on 150 IC’s for better yield and functionality

Laid out 256 array decks and frames for standard packages for cost reduction and TAT.

Managed and laid out all fiducials as the fab required, Nikon/ASML/GCA

Reduced Job intervals by 20% and GAP library TAT by 33%

Documented processes and procedures for ISO 9000 RETICLE/FRACTURE/TAPEOUT ENGINEER

LUCENT, ALLENTOWN, PA

1996- 2000

Functioned as a Job Deck Planner and Frame/Wafer Engineer to create frames with IV testers/litho marks and reticle layout

Wrote UNIX scripts to reduce manual errors and TAT.

Led Waveguides, HPIC, BICMOS and legacy technologies tape-out procedures and functions.

Used CATs fracture to convert GDS to a binary format

Created CATs include files using Boolean operations and compensations

Engineered and maintained custom library for legacy technologies

Documented processes and procedures for ISO 9000

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