Post Job Free

Resume

Sign in

Component Design Engineer

Location:
Chandler, AZ
Posted:
September 22, 2015

Contact this candidate

Resume:

Jimmy Rojas Carranza

ELECTRONICS ENGINEERING

*** * ******** ******, *** Cervantes Community Apt 2141, Chandler, AZ 85224

Cell phone: 480-***-**** – Email: acrs06@r.postjobfree.com

Last time Resume updated: April 2015.

Professional profile

Component Design Engineer with 5 years’ experience in functional test development over core and uncore, main microprocessor functional clusters with 2 paper publications related to Test generators. Electronics Engineering Licentiate Graduated from the Instituto Tecnológico de Costa Rica (ITCR) accredited by Canadian Engineering Accreditation Board (CEAB), responsible, methodic, perseverant, proactive, high English level, open for new ideas and always trying to improve. Interested in digital systems, software development and networking. Used to work under pressure and team player. Software packages knowledge: MS-Windows, MS-Office, Linux and Unix OS as well as high-level programming languages: Perl, C/C++, Java, .NET Platform (C#), Ruby and Python, hardware description languages: Verilog, system Verilog; Strong Assembler skills (IA ASM and Microchip PIC), also basic knowledge on Mechatronic systems with PLC management, and Cisco Networking Academy CCNA 4 modules completed. Basketball Player as a hobby. United States work permit up to date.

Work Experience

-Intel Corporation Costa Rica

Component Design Engineer

January 2010 – Present day.

-Cisco Networking Academy

Networking Program Assistant

February 2007- June 2008.

-Electronics Equipment Seller as a personal business

Cell phones, Computers and Networking equipment.

January 2007- present day

-Independent mathematics and physics professor. 2003- 2005

-Computers support, hardware and software.

-Instituto Tecnológico de Costa Rica.

Numerical Methods teacher’s assistant, 2006-2007.

Recreational Basketball coach assistant, 2008

-Teletica Canal 7, July 2002- December 2002

Engineering Department technical (Technical High School Professional practice)

Installation of the journalists local Network

Teledeportes and Telenoticias Set Restructuring

Formal_Studies

Instituto Tecnológico de Costa Rica

Licenciature degree in Electronics Engineering

Accredited by Canadian Engineering Accreditation Board (CEAB)

Graduation March, 2015

Fundación Tecnológica (FundaTEC)

English scholarship for improving language level

March 2009 – December 2009.

Instituto Tecnológico de Costa Rica, Zapote, Costa Rica.

Certificates

CCNA1 Networking Basics, July 2007

CCNA2 Router and routing basics, November 2007

CCNA3 Switching Basics and Intermediate Routing, March 2008

CCNA4 WAN Technologies, June 2008

Networking Technician CCNA, November 2008

Cisco Systems Networking Academy

Colegio Técnico Profesional Don Bosco

Junior Electronics Technician- December 2002

BACHILLERATO EDUC. DIVERSIFICADA y Técnico medio en electrónica

Languages

Native Language: SPANISH

Language:ENGLISH_90%

Non Formal Studies

Seminar “Electronics Materials Chemistry”

University of Costa Rica

Dr Falman, Michigan University

August 2007

Taller de Verilog

Instituto Tecnológico de Costa Rica

July 2005

Seminar “Man Machine Systems”

Instituto Tecnològico de Costa Rica

Prof.Dr.-Ing.habil- Karl Friedrich Kraiss, RWTH-Aachen University

April-May 2009

Extra Activities

First Division Costa Rica Basketball Player

Team Coyotes de Santa Ana

January 2007- June 2008

University Basketball Player

Team Instituto Tecnologico de Costa Rica

2003-2009

Some Achievements

In Sports:

First Place Costa Rica National Labor games, 2010,2013

Intel Corporation team, Costa Rica

Third Place Central American and Caribe University Sports Games (ODUCC) 2006.

Universidad de Carabobo, Valencia, Venezuela.

First Place Costa Rican University Sports Games (JUNCOS), 2006.

Universidad Nacional de Costa Rica, Heredia.

First Place Costa Rican University Sports Games (JUNCOS), 2004

Instituto Tecnológico de Costa Rica, Cartago.

Better shooter National Students Sport Games, 2002

Sagrado Corazón de Jesús High School, Cartago, Costa Rica.

Central American Salesianos Sports Games Second Place, 2000

Santa Cecilia High School, San Salvador, EL Salvador.

Academics:

Collaboration, classmates respect and honorably represent of the Institution Recognition,

2002 Graduation Technical Don Bosco High School.

General First Place Technological and Scientific Fair EXPOTEC

Project: Electronic Scoreboard

Technical Don Bosco High School. November 2001.

General Second Place Technological and Scientific Fair EXPOTEC

Project: Electronic Scoreboard Prototype

Technical Don Bosco High School. December 2000.

Some knowledge and projects

Software

MS-Windows, MS-Office

Unix OS 5 years’ experience

Verilog, system Verilog, Xilinx HDL (Hardware Description Language)

IA32 Assembler, AVX3 512 instruction set.

Modelsim (Verilog Simulator )

MATLAB, models development Software and Mathematical simulations of physical Systems

PICC, Microcontrollers compiler.

Java, C/C++,Visual C#, High-level languages.

PSpice, Workbench, Multisim, circuit simulators

Packet Tracert, Networking simulator

Fluid Sim 3.6.Hydraulics and Neumatics simulator

STEP 7, PLCs programming software

Intel Software.

Stargate, Testgen, ASTRA, AZTEC, Archsim: For functional test development over Intel Core and Uncore.

Projects

University projects

Three-phase engine monitor and temperature control, Ingenio el Palmar Miramar with USB transfers and Ethernet comunication, PICC, Visual C#.

DTMF tones control system telephone prototype, and RF communication. PICC.

Transport delay control temperature, PICC.

AC three-phase voltage controller, analog system

DC Engine Speed Control, analog system.

Drinks machine Prototype, Xilinx, verilog

Intelligence Stop light prototype, Xilinx,verilog

16 bits Microprogrammed Controller, Xilinx.

Technical Revision Automotive Simulator (RITEVE), C

University Assistant Project:

Digital images convolution process acceleration with an effective CACHE use, the SSE instruction set and multicore systems with parallel programming, over the computer vision library LTIlib-2 build in C++,and Linux as an operative system involve 2010.

Electronics Engineering Graduation Project:

Un-deterministic states sources tracker or X-tracker over digital circuit simulations. Automatic X-validation tool 2014.

Intel experience

General Experience: 5 years as functional test developer, working with Verilog, Perl, IA Assembly languages, CPU micro-architecture, good communication with design team.

Functional Test writing Experience:

-Worked in HVM readiness for IVT and HSX in uncore and for SKX core

-Clean X routine owner for JKT and IVT which provides a deterministic state for the microprocessor. Santa Clara California assignment to work closely with silicon Debug and design team to get the processor X-free for signature mode.

-Functional test writer for several uncore cluster like: Home Agent(HA),Memory Controller (MC) and Cache Box (CBO) clusters for Server products like JKT, IVT, HSX. Worked enabling and validating features for DDR4 technology

-Fodder content developer for speed path detection over SKX.

-Functional test writer for Several Core cluster like: Medium Level Cache (MLC) as content owner and Out Of Order (OOO), enabled a new exclusions flow for the whole core environment, which provided a chance to remove more faults from the fault list.

-Stargate product owner for SKX: Owner of the test tool enabling for SKX.

-Stargate developer for CBO in SKL uncore TW project and MLC in SKL Core project

-THR over IVT, debug several failing units in post silicon for Ivytown Server, use of AFD(Array Freeze Dump) to obtain information of the failing unit and based on architecture knowledge debug the logs, Python scripting for log extraction.

-DFX knowledge features, for Memory controller, IIO, and Core for helping the test development strategy.

DFX knowledge: IIO loopback, MC WDAR(Write Data Always Response), QPI ATM(Address translation Mode), VISA for improving signal observation, all these experience gotten while working on functional test writing for uncore server products like JKT (Jaketown), IVT (Ivytown) and HSX (Haswel-Server) all related to XEON family. Core EXE DFX for moving traffic across the FMA5 instead of FMA0.

Observe-ability experience: Increasing MC observe-ability signals trough PMONs, knowledge on a tool for finding observe-ability issues for any generic design called Multi-thread tracer. Proposed to design the addition of scan-outs in the core MLC in logic related to error detection which presented a bunch of signals with observe-ability issues.

Core experience:

-Test and validation of latest 2014-2015 IA (Intel Architecture) Instruction set called AVX3 and new unit FMA 512 (Fused Multiply and Add) instructions. Functional test development for MLC (Medium Level Cache).

Product owner enabling of the model and content for SKX Big core with 16 ways enabled, new MLC design.

Assignment to Israel for bringing all the Core information and Architecture trainings to Costa Rica team, in order to start a new group for Functional test development over Core.

Memory Controller Experience:

- Developed a new strategy for functional test development related to multiple MC's placed in HSX design and multiple channels per MC, so the test writer just need to develop the scenario for one channel in one MC, and the scenario will be replicated across all the channels and MC's, developed in Perl and Testgen as test development tool.

- Also found a lack of deterministic test development to all the ranks and banks in MC, so Jimmy developed an approach to hit every one of them, increased the coverage by 5% when it was at ~65%, to do that Jimmy found some bits really difficult to map due to another feature enabled behind.

- Enabled for the first time in the functional test development team, Isochronous transactions, in order to manage traffic for different priorities, this enabling required to talk to several architecture experts in CBO,HA, MC and IIO.

- Pending paper proposal due to all conferences cancelation on 2014 for new functional test development over MC when the number of MC's and channels get increased and configurations requires to be replicated across all of them.

Stargate Experience:

- Assignment to Israel on January 2014 to learn its usage and meet the developers.

- 1.5 years’ experience at functional test writing over Stargate for core and uncore.

- Tool owner for SKX enabling in 4 ways and 16 ways big core.

- Stargate and test writing advisor for all the core functional test writing team.

- Costa Rica Representative at Stargate working group, with several site members.

Publications

-Multi-thread and Multi-core SKU (Stock Keeping Unit) independent test content generator. IMEC 2013, Create 2013, PSLE 2012, ATM Tech event 2013. Which provided 3% yield improvement for IVT project.

-Stargate – Shift left & breakthrough Functional Core Test Content Development across Client-Server-SOC. Accepted to PSLE 2015.



Contact this candidate