SAVITANANDAN PATIDAR

E-mail: acriy3@r.postjobfree.com

Phone No: +91-957*******

AREA OF INTREST

Analog & Digital Circuit Design

Industrial Automation, Robotics

Embedded System

CAREER OBJECTIVE

As an Electronic Engineer seeing an employment opportunity to fulfill the goal of employee from learning opportunities and responsibility can make long term commitment. Willing to work as a key player in challenging & creative environment of existing technology. QUALIFICATION COMPLETED

2012-2015

Vishwakarma Govt. Engg.

College, Ahmedabad

GTU

85.80 (9.10 CPI)

M.E. (Signal Processing & VLSI

Technology)

2008-2012 SVCE, Indore RGTU

74.25 B.E.( Electx. & Communication)

2008

School for Excellence,

Khargone

BSEMP 79.50 Class XII (Science Stream)

2006 SVM, Khargone BSEMP 83.40 Class X (General Stream) NATIONAL LEVEL EXAMS

GATE-2015 : 88.59 Percentile

GATE-2013 : 92.74 Percentile

M.E. THESIS

“Ultra Low Temperature Performance Modeling For 180nm MOSFET Technology” EXPERIENCE

Good knowledge in analog & digital design circuits in tools like CADENCE VIRTUOSO, Ng- Spice, Cool-Spice and P-Spice

Knowledge of Digital circuit design, RTL design and synthesis at Xilinx platform using VHDL.

Participated in CADENCE VIRTUOSO Workshop at SAC ISRO Ahmadabad

Testing and Characterization of analog circuit like OPAMP, Bandgap Reference Circuit, ADC, Analog Switches and MOS Devices

Teaching Assistantship duties under supervision of VGEC, Chandkheda faculty SPACE APPLICATION CENTRE, ISRO, AHMEDABAD- (Dept. of Space, Govt. of India): Position: Project Trainee

Duration: 15-July-2014 to 25-may-2015 (11 Months)

PROJECTS UNDERTAKEN IN COLLEGE

Advisor: Dr. R.A. Thakker Mr. Hari Shanker Gupta

HOD, VGEC, Ahmedabad

Mr. Hari Shanker Gupta

Scientist, SAC ISRO, Ahmedabad

Development of Cryogenic MOS models for space application

Simulation Tool - CADANCE VIRTUOSO

Technology - UMC 180nm

Design of automated measurement system for device characteristic using NI-LABVIEW

Measurement of MOS device performance at temperature (-196ºC and 21 C) using Package level & Die-level Techniques

Parameter extraction for different MOSFET devices at points of temperature

MOS Modeling for Cryogenic Temperature by Parameter Tuning & Sub-circuit Modeling TECHNICAL SKILLS

Automation & Controlling Tools: NI-Labview, Psim, Pico-soft

Operating Systems : Windows 7/8/XP

Programming Languages: Basics of C, C++, and VHDL

Layout Tools: MicrowindLite

Computational and Design Tools: Xilinx platform (For RTL design and synthesis)

Circuit designing & Simulation Tools: Cadence-Virtuoso, Ng-Spice, Multisim

DSP & Image Processing Tools: MATLAB, Origin9Pro

Instrumentation: AWG, DMM,FG, Power Supply, CRO, PCB Mounting & Handling ACHIEVEMENTS

Selected as an INTERN at Space Application Centre ISRO, Ahmadabad

Participate in ‘‘Fundamental Course in Rational Rhapsody’’ by IBM Career Educ. Program PUBLICATION

Publication of paper entitled “The Art of Compact Modeling”, published in ‘Technix International Journal for Engineering Research’, Vol 1, issue 11, June 2015.

Publication of paper entitled “SNR Improvement for monochrome detector”, published in

‘International Research Journal of Engineering and Technology’, Vol 2, issue 4, July 2015. PERSONAL PROFILE

Name Savitanandan Radheshyam Patidar

Address Village-Ubadi, Post-Aghawan, Dist- Khargone (M.P)- 451001 REFERENCES

DECLARATION:

I hereby declare that the above-mentioned information is correct up to my knowledge. PLACE: Currently in Indore or immediate to relocate anywhere in India

(Savitanandan Patidar)

Date of Birth

October 20, 1990

Gender Male

Known Languages English, Hindi, Gujarati, Nimadi . Mr. Hari Shanker Gupta

Scientist, SFED SEDA

SAC ISRO, Ahmedabad

Ph: 079-********, 4368

Email: acriy3@r.postjobfree.com

Dr.U.B.S.Chandrawat

Principal

SVCE, Indore

Mob: 093********

Email: acriy3@r.postjobfree.com

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