SUNIT KUMAR SHARMA

Mobile: 080********

E-mail: acrhmw@r.postjobfree.com

Objective

A challenging position in a progressive organization where I can prove my self & performance and contribute towards the development of the organization.

Summary

Comprehensive knowledge in the areas of ASIC Design & Verification. Underwent training in Verilog, System Verilog & UVM methodology at Maven Silicon Softech Pvt. Ltd., Bangalore.

Keen interest in the areas of Digital VLSI Design & Verification, System Design, RTL Design and Semiconductor Devices (Simulation & Modelling)

An effective communicator with strong analytical, problem solving & interpersonal skills

Education

1. B.E. (Electronics & Instrumentation) from IIMT College of Engineering Uttar Pradesh Technical University with 58.28% in 2012.

2. 10+2 from U.P. Board securing 69.00%.

3. Matriculation from Sacred Heart Convent School under C.B.S.E. Board, securing 60.21%.

Technical Purview

HDL & Methodology: Verilog HDL, System Verilog, UVM

Synthesis Tool: Xilinx ISE Design Suite 13.4.

Pre layout Simulator: QuestaSim (Mentor Graphic)

Scripting Language: Shell (Make file)

Operating systems: UNIX & Windows

Protocol: GPIO(General Purpose Input-Output),SPI(Serial Peripheral Interface)

Design Project: AHB to APB Bridge Design using verilog.

Current Project: UART verification by UVM.

Projects Handled

Title: AHB TO APB BRIDGE DESIGN

Period: 1MONTH

HDL: Verilog HDL

EDA Tools Used: XILINX 14.1

Description. AHB works on high frequency whereas APB works on low frequency. For faithful communication between AHB TO APB A Bridge has been designed to synchronize between AHB and APB components

Role:

To synchronize between two clocks to avoid data loss.

Introducing pipelining implementation so that APB components gets enough time to collect data sent from high frequency AHB.

Coding the FSM according to the Protocol which consists of both read and write operations.

Title: UART Verification

Period: 1 MONTH

TB Methodology UVM

EDA Tools Used: QuestaSim

Description: UART provides serial communication capabilities which allows communication with modem or other

external devices.

Role:

Identifying the ports and writing sequences to check the working of each port.

Designing the architecture of the class based verification environment using SV & UVM

Developing various test cases to verify RTL module using SV & UVM

Capturing functional coverage for verification signoff

Title: GPIO Verification

Period: Since 03’15-04’15

HDL: Verilog HDL

TB Methodology: UVM

EDA Tools Used: QuestaSim

Description: The GPIO IP core is user-programmable general-purpose I/O controller. Its use is to implement functions that are not implemented with the dedicated controllers in a system and require simple input and/or output software controlled signals.

Role:

Identifying the ports and writing sequences to check the working of each port.

Created the architecture for the class based verification environment using SV & UVM

Developed various test cases to verify RTL module using SV & UVM

Setting functional coverage for verification signoff

Title: Verification of Router 1x3

Period: 1’15-02’15

HDL: Verilog HDL

TB Methodology: UVM

EDA Tools Used: QuestaSim

Description: The project included a router, a device that forwarded data packets between computer networks. Based on the predefined protocol, it drives incoming packets to any one among the three output channels based on the address field contained in the packet header. The router accepted data packets on a single 8-bit port and routed them to one of the three output channels, channel0, channel1 and channel2

Role:

Architecture the class based verification environment using SV & UVM

Prepared various test cases and verified RTL using SV & UVM

Involved in generating functional coverage for verification signoff

Certification

Completed a Certification Course in System Verilog Based Advanced Verification Course from Maven Silicon Softech Pvt. Ltd., Bangalore and underwent hands-on training in Verilog, System Verilog and UVM Modules.

Trainings

ASIC Design and Verification Training (6 months).

Current Designation

Project Intern at Maven Silicon Softech Pvt Ltd from 12/06/2015.

Workshops

Attended workshops on:

oParticipated in ‘VLSI Technology’ workshop conducted in our college campus by CETPA Softronics,Nioda.

oAttended a five day workshop on ‘Soft Skills’ held in our college campus.

Extramural Engagements

Took part in various University Level sports.

Organized various seminar and workshop in the Department.

Personal Details

Languages Known: English, Hindi . Bangla.

Address: #113, Sevenhills Pg, Arekere, Bannerghatta road, Bangalore -560076

Declaration

I hereby declare that the above details are true to the best of my knowledge.

Date: 17.03.2015

Place: Bangalore, India. Sunit Kumar Sharma

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