Mis: SAROJINI HOOGAR S

Email id: acre0h@r.postjobfree.com

Mob: 741*******

CAREER OBJECTIVE:

I am seeking for challenging position Core Company to work on real time projects and hence to contribute better worth service and also to learn upcoming technologies for gaining knowledge.

CORE COMPETENCY:

Basic C, Verilog, Digital Electronics, Fundamentals of VLSI, OS.

EDUCATION :

DEGREE

DISCIPLINE

INSTITUTE

UNIVERSITY

YEAR OF PASSING

AGGREGATE

M.tech

Signal processing & VLSI

SBMJCE Kanakapur, Bangalore

2015

82.98 %

BE

Electronics & Communication

BLDEA's CET, Bijapur

2013

71.89 %

12th

Science

RMG College Mudhol

2009

84 %

10th

State syllabus

NAVODAYA school, Hebbal

2007

82.88 %

ACADEMIC PROJECTS:

Title:

1) BOOTH MULTIPLIER: Design of high performance booth multiplier using Xilinx tool (B.E final year project).

Description:

Description: Multipliers are key components of many high performance systems such as FIR filter, microprocessor, DSP systems, etc. Booth multiplication allows for smaller, faster multiplication circuits through encoding the signed numbers by 2’s complement, which also standard technique used in chip design and provides significant improvements by reducing the number of partial product to half over along multiplication technique. So speed of multiplication increases, hence circuit performance increases.

Tools Used :

Xilinx

Title:

2) DOUBLE TAIL COMPARATOR: design and analysis of low voltage and low power double tail comparator (M.tech 1st sem mini project).

Description:

Description: Comparator is one of the fundamental building blocks in most analog-to-digital converters (ADCs). The new dynamic comparator is proposed, where the circuit of a conventional double-tail comparator is modified for low-power and fast operation even in small supply voltages. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced. This is done by adding tails at top and bottom.

Tools Used :

Mentor graphics

Title:

Foggy Image Enhancement Using Wavelet Decomposition, LUM Filter & histogram equalization (M.tech 2nd sem mini project)

Description:

Description: As one of the most common weather conditions, fog have whitening effect on the scenery thus drops the atmospheric visibility which leads to the decline of image contrast. So wavelet technique is used to get low & high frequency components, then low frequency component is passed through LUM filter then histogram equalization is used to increase contrast. Finally both high & equalized components are processed with inverse wavelet transform to get fog free image.

Tools Used :

MATLAB

Deliverable/Challenges Faced:

Reducing noise & fog from image.

Title:

: Programmable DMA design using advanced high performance bus protocol.

Role:

Lead

Organization:

Global Research Innovation & Development India, BANGALORE

Description:

The 8237A programmable DMA is specifically designed to transfer the data at high speed. Its primary function is to generate the peripheral request and sequential memory addresses, which allows the peripherals to read or write data directly to or from the memory. By cascading the 8237A the number of channels is extended to n number of channels. Different addressing modes & transfer modes are used. Best scheduling algorithm is used to resolve the priority of the 8 channels. This DMA controller is better than 8237A in terms of performance.

Tools Used :

Xilinx 12.2( Verilog coding )

Work Experience:

Organization:

Global Research Innovation and Development, Bangalore

Designation:

Intern (ASIC DESIGN)

Duration of Project in Months:

Oct 2014 to present

CURRICULAR ACTIVITIES

Presented ‘DMA controller design using AHB protocol‘ Paper in “International Association of Engineering & Technology for Skill Development ICAER, Vijayawada – 2015. Published in “International Journal Of Engineering And Computer Science (IJECS)”.

Presented paper in National Conference on "Emerging Trends in Engineering & Technology and Applied Research" on July 10, 2015 Sponsored by VTU, Belgaum Organized by M. S. Engineering College, Bangalore

PERSONAL PROFILE:

Name

:SAROJINI HOOGAR S

Date of Birth

: 7/May/1990

Address

:SAI BALAJI PG, 1st cross, 3rd main, BTM 1ST STAGE, Bangalore – 560010

Father Name

: SHANKAR HOOGAR

Nationality

: Indian

Sex

: Female

Languages known

: English, Kannada, Hindi

DECLARATION:

I do hereby declare that the above information is correct and true to the best of my knowledge and belief.

Place: Bangalore yours faithfully

Date

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