Richa Sharma

***, *-* ********, **** Ganga Society

Opposite RTO(Alandi Rd), Yerwada,

Pune-411006

Contact: acrd8o@r.postjobfree.com

Mob: +91-954*******

Objective

To be a part of an organization which would provide me with an opportunity to work to the best of my potential, in turn fulfilling the organizational goals by creating value for it.

Academic Qualification

Qualification

Degree

Year

Institute

Board/University

Percentage

Division

Post-Graduation

M.Tech (VLSI Design)

2014

C-DAC Mohali

PTU

78.5

First

Graduation

B.Tech (ECE)

2012

Rayat Bahra Group of Institutes

PTU

81.1

First

XII

HSC

2008

BBMB DAV Public School, Nangal(Pb)

CBSE

84.0

First

X

SSC

2006

BBMB DAV Public School, Nangal(Pb)

CBSE

87.2

First

Technical Proficiency

Hardware Description Languages

Verilog,VHDL

Simulation Tools

ModelSim, Xilinx Isim

Synthesis Tools

Xilinx Synthesis Tool (XST)

Design Platform Tools

Cadence Virtuoso Design Suite

Microcontroller

8051, AVR 8515

Microprocessor

8085, 8086, ADSP 2181

Design Kits

FPGA Spartan III Starter Board,FPGA Spartan III-E kit, AVR8515 STK-500 kit, Virtex-5 FPGA Board

Projects Undertaken

M.Tech Thesis Work

Project Title: HDL Design and Synthesis of 32-bit Vedic Arithmetic Unit

Language/Tool: Verilog (Xilinx Project Navigator 14.3, ModelSim SE 5.3f)

Brief Description: As part of this project,a high Speed ALU was designed in which the Arithmetic Unit

Comprising of the adder, subtractor, multiplier, square and cube was designed using the Ancient Indian Vedic Mathematic techniques and the Logical unit was designed using the conventional methods. The 32 x 32 bit multiplier and square entities based on Vedic mathematics was designed and compared with the existing units. The result showed the efficiency of the designed units compared to the conventional units in terms of propagation delay. The 32-bit cubing unit was also designed using the Vedic mathematics sutras. A complete 32-bit Vedic arithmetic unit was designed& functionally verified. Also a 32-bit logical unit was designed & functionally verified using conventional manipulations. At the end, 32-bit Vedic arithmetic and 32-bit logical units were combined into a single top level entity. Results showed the better performance of the designed unit in comparison to the existing conventional ALU. Xilinx ISE 14.3i Suite was used for HDL design entry and synthesis of the proposed arithmetic unit.

M.Tech Minor Projects

Project Title:CRT Controller

Language/Tool: VHDL/ (Xilinx Project Navigator 12.3, ModelSim SE 5.3f)

Brief Description: As part of this project, a CRT controller was designed using VHDL and the response was verified on SPARTAN-3 FPGA. A VGA port was used for the display of the different patterns on the screen by using different colors.

Project Title: UART (Universal Asynchronous Receiver – Transmitter) (FPGA)

Language/Tool: VHDL (Xilinx Project Navigator 12.3, ModelSim SE 5.3f)

Brief Description: As part of this project, a basic UART which is used for serial communication in various microprocessors and microcontrollers was designed using VHDL and the response was verified on SPARTAN-3 FPGA.

Project Title: I2C (Inter-Integrated Circuit)

Language/Tool: VHDL (Xilinx Project Navigator 12.3, ModelSim SE 5.3f)

Brief Description: As part of this project, an inter-integrated circuit used for communication between the two ports acting as a master and slave of a circuit was designed using VHDL. In this single data bus was used for transferring the information from one port to the other.

Extra Curricular Activities

●Participated in state level Hockey tournament

●Participated in intra college Debate competition

●Worked as a member of NSS

●Participated in Dance competitions at school and college level

●Attended workshop by Synopsys on analog tool and participated in national level Analog design contest

●Published paper in IEEE Conference.

Personal Profile

Date of Birth : 23rd Sep, 1990

Gender : Female

Marital status : Married

Strengths : Highly motivated, Self-confident and Hardworking

Languages known : English, Hindi and Punjabi

Interests : Watching TV, Playing Hockey and Chess

Contact this candidate