ANKIT DWIVEDI

**** ******* ***, *********, ** ***86 www.linkedin.com/pub/ankit-dwivedi/36/52/663/ acqzw2@r.postjobfree.com 213-***-**** EDUCATION

University of Southern California

Los Angeles, CA

Master of Science

(Electrical Engineering)

GPA: 3.37

May 2015

Relevant Course Work :

Computer System Organization, Network Processor Design and Programming, MOS VLSI Design, VLSI System Design, Internet and Cloud Computing, Design and Diagnosis of Reliable Digital System, Digital System Design – Tools and Techniques Jodhpur Institute of Engineering and Technology

Jodhpur, India

Bachelor of Technology

(Electronics and Communication)

GPA: 81.13/100

June 2011

TECHNICAL SKILLS

HDL and Programming Languages : Verilog, System C, C, C++, VHDL Tools and Packages : ModelSim, Cadence Virtuoso, Xilinx 14.7, NCsim, dccompiler, PrimeTime, Cadence Encounter Scripting : Perl, Python

ACADEMIC PROJECTS

Dual Core Network Processor with Hardware Accelerators (RTL/ Verilog/ NETFPGA/ Xilinx/ Perl) www.googledrive.com/host/0B47ai8H-zYjWVGhlR09tVFFKZmM Designed and implemented a dual-core dual thread processor coupled with two hardware accelerators for fast processing of packets, extracting information for data analysis at line speed over controlled network. Each core has a five-stage pipelined RISC processor with a custom MIPS ISA, dual-function SRAM/FIFO memory.

Fault Collapsing,Collapsing,ATPG and Fault Simulation Algorithm (C/ Perl) Implemented ATPG and fault simulator algorithms for combinational circuits in C (ISCAS benchmark) by generating the fault list using fault collapsing (equivalence and dominance) for all single stuck at faults, generating the test pattern for the fault list using D-Algorithm and PODEM and performing Parallel and Deductive Fault Simulation on the provided benchmark circuits and test patterns. DDR2 Memory Controller Design (ASIC Design/ NC Verilog/ Design Compiler/ Encounter) Designed a DDR2 memory controller clocked at 2.6ns in Verilog HDL that would support write and read transactions like scalar, block and atomic to and from the DDR2 SDRAM. Simulated and synthesized the design along with Denali’s DDR2 model using Cadence NC Sim and Design Compiler respectively for 180nm technology and placement and route using Cadence Encounter. 32 Bit Out of order(OoE) Execution Tomasulo Processor (Xilinx ISE/ModelSim/VHDL/Nexys4 FPGA) Designed a 32 bit Out of Order Execution and In-order completion (IoC) Tomasulo processor implemented on Atrix 7 Xilinx FPGA. Implemented Copy-free Check pointing for selective flushing due to branch miss prediction, Free register List (FRL) for efficient implementation of register Alias Table, Branch Prediction Buffer and Return Address Stack for speculative execution, Store Address Buffer for memory disambiguation, Re- order buffer to achieve IoC and Store Buffer (SB) to better utilize the Load/Store Issue queues. Chip Multi-Multi -Threaded Processor Design (Xilinx ISE/ModelSim/VHDL/FPGA) Designed a 32 bit MIPS fine grained Multithread pipelined processor capable of running 4 threads implemented on Spartan-6 Xilinx FPGA. Round Robin prioritizer was used to select the thread after resolving all dependencies. Instruction and Data cache were implemented with non blocking BRAMs by using MSHR (Miss Status Handling Registers) to serve up to 4 Cache misses at a time. General Purpose Microprocessor (Physical Design/ Cadence Virtuoso/ Perl) Designed a 64-bit multi cycle CPU capable of performing arithmetic and logical operations like lw, sw, sub, add, AND, OR and divide. Implemented Power and delay optimization techniques using Dynamic Logic gates, Clock Gating. Perl scripting was used to generate the vector file providing the instructions to be executed. Built schematic and layout of 1024 bit 6T-SRAM memory. FIFO Design (ModelSim/ Xilinx/Xilinx /Verilog/SystemC)SystemC ) Designed and implemented 1 and 2-clock FIFO in Verilog. Designed 1-clock FIFO in SystemC and using pipelined and flow-through BRAM. WORK EXPERIENCE

Directed Research – USC, Los Angeles, US Jan 2015 to May 2015 Responsibility: Studied RAM/CACHE design to find the design with optimum power, delay and area for YIELD improvement. Tools used: CACTI6.5

Systems Engineer - Infosys Limited, Pune, India Feb 2012 to July 2013 Responsibility: Led a team to develop ASP.NET based web portal for management of spaces across the Infosys network in India. Tools and Languages used: C/C++, C#, ASP.NET, SQL, HTML, XML, Web Services, MySQL, MS SQL, Microsoft Visual Studio, Eclipse.