MD AYUB

Masters in Embedded Systems & VLSI Design

Email ID: acqwsf@r.postjobfree.com

Mobile No.:+91-996*******.

CAREER OBJECTIVE:

Seeking a position with an organization where I can contribute my skills for organization’s success and synchronize with new technology while being resourceful, innovative and flexible.

TECHNICAL SKILLS:

CAD Tools : Cadence Tool Suite, Synopsis (VCS), Mentor Graphic, Xilinx ISE, Active HDL, Keil.

Hardware Description Languages : Verilog, Systemverilog, VHDL

Software Skills : C, Basics of OOPs & Scripting.

Platforms : UNIX, Linux, Windows.

Architectures : NXP1768, µP 8086, µC 8051.

Assembly Programming : NXP1768, µP 8086, µC 8051.

Hardware Expertise : ARM Cortex M3 (NXP1768) SOC Board

Mathematical Tools : MATLAB.

Package : MS Office {Word, Excel, PowerPoint}

ACADEMIC CREDENTIALS:

Master of Engineering (M.E) VLSI Design & Embedded Systems from Vasavi College of Engineering (OU) 2013

Bachelor of Technology (B.Tech.,) Electronics & Communication from Ayaan College of Engg & Tech., (JNTUH) 2010

Intermediate Mathematics, Physics, Chemistry (M.P.C) 2006

CERTIFICATIONS:

Embedded System Design using ARM cortex M3 at CDAC Hyderabad

Digital Design & Verification front-end at Seer Academy Hyderabad

EXPERIENCE SUMMARY:

Intern at Dreamz Infotel(2012-2013):

Worked as an intern at dreamz infotel for Post-graduation project titled “Coverage Driven Constraint Random Verification using SystemVerilog”

During my tenure as an Intern I have equipped with the respective skill set as follows

Experience in RTL Design and Synthesis using Verilog.

Functional verification experience at block, sub-system level using HVL (SystemVerilog) over multiple ASIC/FPGA programs which mainly involving tests architecture, test design and planning, test implementation and functional coverage.

Proficient in Verilog, SystemVerilog, OOPs concept and knowledge on Make File

ACHIEVEMENTS:

Qualified GATE 2011.

Published and Presented a Paper Titled “MULTI SPECTRAL IMAGE FUSION OF MEDICAL IMAGES” in the proceedings of “FACT-2011” a National Conference in December 2011.

Participated 2-day in 25th International Conference on “VLSI Design” and 11th International Conference on “Embedded Systems” in January-2012.

Participated in 2-day National level workshop on “SIGNAL AND SIGNAL PROCESSING SIMULATION using MATLAB” in July, 2011.

PROJECT PROFILE:

M.E Final Year Project

1) Title: Coverage Driven Constraint Random Verification of RTL design using SystemVerilog

ABSTRACT: Constraint-driven test generation allows users to automatically generate tests for functional verification. Random testing can be more effective than a traditional, directed testing approach. By specifying constraints, one can easily create tests that can find hard-to-reach corner cases. Constraint Random verification is being widely accepted as a key technology in the pre-silicon validation of system-on-chip (SOC) designs.

Coverage Driven CRV combines automatic test generation, self-checking test benches, and coverage metrics to significantly reduce the time spent verifying a design and ensuring thorough verification using up-front goal setting

CAD Tool: Modelsim & Questa sim (Mentor Graphics)

HDL: Verilog HVL: Systemverilog

Operating system: UNIX (cygwin)

M.E Semester projects

Project Title 1:

Design of Two stages Operational Amplifier with single ended output

CAD Tool : Cadence Virtuoso Schematic Editor

Project Title 2:

Design Gold code generator for CDMA spread spectrum

CAD Tool : Cadence NC Verilog, RC Compiler

Graduate Project Title :

Multi Spectral pixel level Medical Image Fusion using Wavelet

CAD Tool : MATLAB

PERSONAL SKILLS:

Positive attitude, self-confidence and eagerness to learn.

Excellent problem solving skills with a strong technical, academic back ground and good interpersonal skills.

Enjoys interaction with people, organized and like to take challenges, perform well under high level of responsibility.

PERSONAL PROFILE:

Name : Md Ayub

Father’s Name : Md Arif

Sex : Male

Date of Birth : 20th August 1988

Marital Status : Single

Nationality : Indian

Linguistics : English, Hindi & Urdu

DECLARATION:

I hereby declare that the above mentioned information is correct up to my knowledge and I bear the responsibility for the correctness of the above mentioned particulars.

Location: Hyderabad MD AYUB

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