#***, ********** *****,

Cheyyar-******,

Thiruvannamalai Dt,

Tamil Nadu.

Mobile: +91-959*******,

+91-978*******,

Email:acqwli@r.postjobfree.com

Dinesh Kumar.B

Career Objective: A Design and Verification Engineer position in an organization seeking committed and fast learner with knowledge of Verilog, test benches & verification techniques, along with hands on experience on Cadence tools.

Summary: Exceptionally talented Engineer with Master of Engineering in VLSI design and excellent academic record. Committed to the highest levels of professionalism and excellent interpersonal skills. Demonstrated expertise in Verilog HDL and front-end Cadence based ASIC flow in Post Graduate project work. Seeking a challenging role in ASIC design and verification.

Educational Qualification:

Completed M.E. VLSI DESIGN with 8.5 CGPA at Adhiparasakthi Engineering College, Melmaruvathur in 2015

B.E. Electronics and Communication Engineering with 6.12 CGPA at Kalsar college of Engineering, Chennai in 2012

H.S.C with 80% from Govt.Boys.Higher Secondary School, Cheyyar in 2008

S.S.L.C with 81% from Govt.Boys. Higher Secondary School, Cheyyar in 2006

Technical Profile:

Programming Language : C, C++, Embedded C

HDLs : VERILOG HDL, VHDL, SYSTEM VERILOG, NCVERILOG

Scripting Languages : Perl, shell, Python, Tcl

Programming Platform : Cadence Tool Suite, Mentor Graphics, Synopsys, Xilinx ISE, PSPICE

Protocols/Methodology : OVM, UVM, VVM, AHB, PCI, SATA, USB (V2.0/3.0)

Area of Interest : VLSI Verification & ASIC Design

Operating Family : LINUX, Windows Family

Courses & Training:

Have finished DCA (DIPLOMA IN COMPUTER APPLICATION, with UNIX and C, C++) from APTECH, Cheyyar.

Have undergone in-plant training in BSNL, Chennai Telephones and also in QuicCalls Pvt.Ltd, Chennai.

Project UG:

Project: “PUBLIC TRANSPORTATION INFORMATION USING GSM QUERY RESPONSE SYSTEM”

Tool used: Embedded kit

Operating System: Windows 98 or Higher Editions

Description: This project is used to help and guide the users to reach their destinations by public transportation using simple SMS query response system.

Project PG:

Project: “EFFECTIVE BIST ARCHITECTURE TO REDUCE HARDWARE OVERHEAD IN DIGITAL CIRCUITS”

Tool used: Cadence Tools & Model sim

Operating System: Red hat (LINUX)

Description: The Project involves in DFT (Design for Test) technique BIST (Built In Self Test) architecture which gives best results in low hardware overhead and high speed in Digital Design. Concurrent BIST is used to provide better result than existing BIST schemes. This scheme is capable of test and repair (Built In Self Repair) faults in Digital Circuits. This project design over rides the existing design results better in two properties CTL, Hardware overhead.

Personal Profile:

Name : Dinesh Kumar.B

D.O.B : 1st January 1991

Nationality : Indian

Languages known : Tamil & English (To read, write and speak)

Interested in : Net surfing, watch movies, Reading books and listening to music.

Achievements:

Have Presented ”EFFECTIVE BIST ARCHITECTURE TO REDUCE HARDWARE OVERHEAD IN DIGITAL CIRCUITS” paper on National Level conference titled as “National Conference On Model Electronics “ at Jeppiar Institute of Technology, Sriperumbudur

Have Published paper ”EFFECTIVE BIST ARCHITECTURE TO REDUCE HARDWARE OVERHEAD IN DIGITAL CIRCUITS” on International Journal of Innovative Science, Engineering & Technology, Vol.2 Issue 4, April 2015. Pp 862-865.

Have participated in National level conference on INFORMATION, COMMUNICATION &

NETWORKING (NCICN – 2012) conducted by Easwari engineering college.

Declaration:

I hereby declare that the above-mentioned information is correct up to my Knowledge and I bear the responsibility for the correctness of the above mentioned Particulars.

Place : Signature:

Date : (Dinesh Kumar.B)

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