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PROFESSIONAL SUMMARY:

Hands on experience with FPGA tools Xilinx, Actel

Expertise with VHDL, Verilog-HDL languages

Hands on experience with System Verilog

Highly efficient in understanding client’s requirements and converting them into System developments.

Having excellent problem solving skills, with good Analytical and Decision making

And team building skills.

Experience in Circuit designing, Circuit simulation, and Schematic designing.

Highly motivated and ability to work both independently or as part of a team.

TECHNICAL HIGHLIGHTS:

Strong Coding and debugging skills.

Hands on experience with Modelsim and Questasim

Expertise in RTL coding,simulation and synthesis

ACADEMIC PROFILE:

B.Tech in Electronics and communication from Sri Sivani College of Engineering and Technology with 54.1% (2007-14).

Intermediate from Board of Intermediate Education with 75% of marks (2005-07).

S.S.C from State Board of Secondary Education with 77.5% of marks (2004-05).

Project handled in B Tech:

Project 1

Title: ENCRYPTION AND DECRYPTION OF DATA USING AES ALGORITHM

Description : The Advanced Encryption Standard (AES) is a specification for the encryption of electronic data established by the U.S.National Institute of Standards and Technology (NIST) in 2001. This algorithm is used whenever high security is required with high key length. It developed for the research develop in the college.

Tools and languages used:

Hardware language used: Verilog HDL

Simulation tool used: Modelsim 6.4c

Synthesis tool used: XILINX ISE 10.1I

Roles and Responsibilities:

Design document development

RTL implementation

Simulation and synthesis of the RTL design

Identification test cases and its development using verilog

Project 2

Title: I2C slave controller develop using VHDL

Description : A typical embedded system consists of one or more microcontrollers and peripheral devices like memories, converters, I/O expanders, LCD drivers, sensors, matrix switches, etc. The complexity and the cost of connecting all those devices together must be kept to a minimum. The system must be designed in such a way that slower devices can communicate with the system without slowing down faster to satisfy these requirements a serial bus is needed. The I2C bus uses two wires: serial data (SDA) and serial clock (SCL). All I2C master and slave devices are connected with only those two wires. Each device can be a transmitter, a receiver or both.

Tools and languages used:

Hardware language used: VHDL

Simulation tool used: Modelsim 6.4c

Synthesis tool used: XILINX ISE 10.1I

Roles and Responsibilities:

Design document development

RTL implementation

Simulation and synthesis of the RTL design

Identification test cases and its development using VHDL

Project 3

Title: Development of Test bench for the 64x64 multiplier using System verilog

Description : The verification environment is essential one for any design. In this project develop the generic test bench environment for any type of multiplier.

Tools and languages used:

Verification language used: System Verilog

Simulation tool used: Questasim 10.4 c

Roles and Responsibilities:

Test plan document development

Identification test cases and its development using system verilog

Personal Details

Name : Sreekanth.Danda

Father’s name : D.Manohara Rao

Date of Birth : 22-08-1990

Gender : Male

Marital Status : Single

Languages Known : English, Telugu

Nationality : Indian

Hobbies : surfing the internet for new articles

Address : GandhiNagar Street,

Ponduru,

Srikakulam Dist,

Pin: 532168

Sreekanth

Date:

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