CURRICULUM VITAE

Name : Rajuprasanth R

Mobile : +917*********

Email : acqw9v@r.postjobfree.com

Career Objective

To obtain a position that will enable me to use my strong organizational skills educational background, and ability to work well with people.

Qualification Summary

A judicious professional with 2.1 years’ of experience in Hardware Description Language and development on ASIC applications.

Experience in MentorGraphicsModelsim 10.1&Xilinx ISE Design 13.2, Verilog and Systemverilog.

Skilful in IP development using Verilog and Systemverilog with proficiency in using simulation and design packages such as MentorGraphics&Xilinx.

An effective communicator with honed relationship management, analytical, logical and problem-solving abilities.

Experience Summary

Currently working as a RTL Design Engineer in Spiro Solutions Pvt. Ltd, Chennai since June-2013.

Expertise in Design and Development of modules for the ASIC Applications.

Contributing to the design, development, testing and debugging of the project.

Skills Summary

Domain Knowledge - VLSI, Fundamentals of Digital Electronics, CMOS Technology, Basics in Micro controllers & Analog Mixed Signal Processing.

Development Tools - Modelsim 10.1, Xilinx ISE Design 13.2 & Tanner EDA Tools 14.1

Languages - C, OOPs, PERL, Verilog, System verilog.

Protocol - UART, SPI, I2C

Specialization - Designing Intellectual Properties and creating Testbench, Designing Verification IP for ASIC Applications.

Education Summary

Bachelor of Engineering in Electronics & Communication (May 2013) from C.M.S College Of Engineering, Anna University with 76.50%.

HSC from K.V.S Higher Secondary School, virudhunagar in March 2009 with 68.33%.

SSLC from K.V.S Higher Secondary School, virudhunagar, in March 2007 with 72.40%

Developed Projects

1.Project:

Parallel AES Encryption Engines for cryptography application

Environment OS:

Windows XP, Windows 7

Environment:

Model sim 10.1 & Xilinx ISE design 13.2

Hardware:

FPGA Spartan 6

Role:

Team player/Design engineer

Designation:

RTL design engineer

Team Size:

4

Description:

This project involves design and implementation of Advanced encryption standard has been developed using Rijndael algorithm to perform for cryptography application. AES encryption process means our data will be change into other data with using key. AES decryption process means retrieve the original data. Finally AES is best one of the cryptography application.

Roles and Responsibilities:

To interact with client for specification related queries.

Involvement in database design.

Development activity as module wise in iterative manner.

Involved in defect fixes and implementing change requests frequently as indicated by the clients.

2.Project:

Novel core supporting Compression using CSDA Technique to reduce Hardware Complexity

Environment OS:

Windows XP, Windows 7

Environment:

Model sim 10.1 & Xilinx ISE design 13.2

Hardware:

FPGA Spartan 6

Role:

Team player/Design engineer

Designation:

RTL design engineer

Team Size:

4

Description:

This project involves design and implementation of Multi Standard Core has been developed using CSDA technique to perform compression for image processing. To reduce the number of gate counts, in this project, we using the Factor Sharing and Distributed Arithmetic to replacing the non-zero elements to zero and utilizing the same resources, the complexity is reduced. Finally, we reduced the area for less power consumption.

Roles and Responsibilities:

Involved in requirement gathering and document analysis.

Developer, Designer.

Improve the system throughput.

Used verilog for design and creating testbench.

Personal Data

Father’s Name - Ramaraj S

Sex - Male

Languages Known - English, Tamil, Telugu (speak)

Phone - 770-***-****, 900-***-****

Marital Status - Single

DOB - June 8, 1992

Passport no - M3794593

Expiry date - 20/11/2024

Nationality - Indian

Hobbies - Cricket, Chess, Music

Contact Address - No: G1, Sri Vari apartments, officers Colony, West street, 1st street,

Adambakkam, Chennai – 600088.

Permanent Address - No: 1/73, Chittoor (Post), Thirumangalam (TK), Madurai (DT)-625707

Declaration

I do hereby declare that the particulars furnished in this resume are true, complete and correct to the best of my knowledge and belief.

PLACE : Chennai

DATE : Rajuprasanth R

Contact this candidate