Ashok Tiwari

Mobile: 908-***-**** E-mail: acqv5z@r.postjobfree.com

Career Summary

Highly motivated and enthusiastic Electrical Engineer with a specialization of Digital Systems

(Logic design, Physical Design, Communication/Networking). Seeking Full-time/Part- time/Contract opportunity that will utilize my Master’s education as well my past experience.

Meritorious, scholarship holder with MS in EE with zeal to grow in the field of Electronics and software development.

Good knowledge of programming in Verilog HDL, Python, C, C++, C#.

Experience on implementing/supporting live projects using .Net, MS-Access/Ms-Sql Server & Oracle.

Self-motivated professional with strong communication skills, an ability to learn new things quickly and work as a team.

Academics

MS in EE from Rochester Institute of Technology with 3.33/4.0 GPA score. Courses Undertaken: Design of Digital Systems, Design & Test of Multi-core chips, Design of Experiments for Process Improvement, Analog Electronics, MEMs Evaluation, Data communication and Networks, Error Detection & Correction, Principles of Telecommunication, and Matrix Methods

Graduate Paper: Internet of Things (IoT) – Smart cities

Bachelors degree (Electronics & Telecom) from Mumbai University with 3.15/4 GPA(2009-12)

Diploma (Electronics & Telecom) from Maharashtra State board of Technical Education with 3.5/4.0 GPA(2006-09)

High school from Maharashtra State board of Technical Education with First Class. Technical Skill Set

Programming languages: Verilog HDL, Python, C, C++, C#.

DBMS: Oracle 10g/11g, Ms-Sql 2008/2012, Ms-Access 2010

Operating System: Win-2003 EE-2008-2012, Win-08/Vista, Server RHEL 5.0/6.0

Tools: Crystal Reports, Toad, Sql developer, Cadence Virtuoso, Minitab

Ms-Office: Word, Excel, Access, Outlook, Outlook Express and Power point. Work Experience

theOnedesigns (India) Software Engineer July 2012 to July 2013

Provided technical support for application and associated databases (Oracle/Ms-Sql)

To study Client setup and Implement customized applications as per there need in Multi-User and Single User environment.

Ashok Tiwari

Mobile: 908-***-**** E-mail: acqv5z@r.postjobfree.com

Installing and configuring Oracle/MS-SQL/Access database as per the customized need of application.

Providing training to client’s on various applications.

Scheduling auto backup and testing of existing backup / recovery strategy.

Solving technical and functional problems on site.

Applying application patches to fix bugs.

Troubleshooting Functional and Technical problems related to customized application at client place. Creating Users rights to Admin department and higher authority through user manager. Environment: Oracle 11gR2/10g, Ms-Sql 2008R2/2012, RMAN, Toad, Pl/Sql Developer, Exp/Imp, Data Pump, OEM, SQL*Plus, Windows 2003 /2008/2012, SQL*Net, Ex-Ngn, .NET Framework 4.0. Projects Undertaken

DESIGNING OF CROSSTALK AVOIDANCE CODE (CAC) SCHEMES: NOV 2014(RIT)

Three CAC schemes were implemented using Verilog RTL Coding, in order to reduce the energy dissipation in Network-On-Chip (NoC) designs.

The RTL coding was tested by creating a test-bench to monitor whether the output of encoder and decoder of the CAC scheme were according to the input applied. DESIGNING OF MEMORY ARBITER USING VERILOG: NOV 2013 (RIT)

A centralized two level bus arbiter is built for DTMF (Dual tone Multi-frequency) as an explicit state machine. The arbiter resolves the conflicts of bus control by assigning priorities. The design logic includes giving higher priority to TDSP (Tiny DSP) module over DMA (Direct memory access) module to access the DMA.

A verification test bench is designed for memory arbiter. The test bench is conditionally compiled to stop the simulation if any DMA or TDSP error occurs. DESIGNING OF TWO STAGE OPERATIONAL AMPLIFIER: NOV 2013 (RIT) Designed a two stage Op-amp circuit that successfully achieves low noise specification and simulated using Cadence Analog Design Environment (ADE) tool as well as carried out the physical implementation (Layout) of the designed circuit.

DESIGNING OF 5-BIT BOUNDARY SCAN REGISTER: OCT 2013 (RIT) The design and physical implementation (Layout) of a 5-bit Boundary Scan Register using a Full Adder in Cadence was successfully performed in a corner cell by hierarchical design approach. CAR COMMUNICATION USING ZIGBEE TECHNOLOGY: 2011-12 (MU, India) Several ZIGBEE nodes were developed covering a particular area of interest under which if the car enters, information about surroundings such as traffic, parking-lots, hospitals were transferred to the car upon request.

Contact this candidate