Thyagarajula Naidu G

Mobile: +91-990**-*****

E-mail: acqmls@r.postjobfree.com

HAVING TIER 2 VISA for UK for 3 Years 2014 Nov to 2017 Oct)

Experience:

Hands on experience on modern verification methodologies such as UVM/OVM

Experience on OOP concepts, System Verilog and virtual interface

Formal verification using SVA & ABV

Experience on storage IP protocols – SD Device, SDHOST and UHSII PHY

Familiar with MIPI protocols – RFFE Master, RFFE Slave controller & MPHY

Developing experience in building verification Environment using OVM/UVM

Experience in creating test environment and BFM models from scratch

Worked on coverage closure, tape out and silicon validation

Very good knowledge on gate level simulations

Experience on Zero Delay & SDF simulations

Good hands on debugging failures in gate level simulations

Hands on experience on writing corner cases & error scenarios using Verilog and System Verilog

Familiar with verification flow and worked on test plan and test execution

Proficient in BFM development in Verilog HDL and Test benches in System Verilog

Experience on regression and coverage generation

Experience in using industry standard EDA tools for the front-end design and verification

Technical Skills:

TB Methodology : UVM & OVM

HDL : Verilog

HVL : Verilog, System Verilog

Verification Methodologies : Constraint driven Verification (CDV)

Assertion Based Verification (ABV)

EDA Tools : Mentor Graphics – Modelsim, Questasim

Cadence – Ncsim, IRUN, ICCR, IMC, RC, LEC

Synopsys – VCS, Verdi

Xilinx – ISE

Altera - Spyglass

Scripting : Perl, Python

Domain : Digital ASIC Verification

Experience:

Employer

Designation

From_Date

To_Date

Fluerdelis Technologies Pvt Ltd

Sr. Engineer

Dec 2009

June 2011

Adventura (A Division of Arasan chip systems) Technologies Pvt Ltd

Verification Engineer

August 2011

May 2013

LSI India Research & Development Pvt Ltd

ASIC Verification Engineer

June 2013

Nov 2014

Test and Verification Solutions Pvt Ltd

Senior Verification Engineer

Dec 2014

Till date

Professional Qualification:

Course/Degree

Year of completion

College/Institution

Percentage

Bachelor of Technology

(Electrical & Electronics Engineering )

May 2009

J.N.T.U Hyderabad

73%

Intermediate

March 2005

Sree Venkateswara Jr. College

88.5%

S.S.C

March 2003

Z. P. High School

86.8%

VLSI Projects:

Project#1: Verified Verilog Behavior model & VAMS model of MPHY AFE using UVM – Block level Verification using UVM

Company

Test and Verification Solutions

Designation

Senior Verification Engineer

Project

Developed verification Environment for Analog equivalent behavior model verification using UVM

Description

Behavior model is fast and accurate simulation of a full chip with the package. But SPICE can take weeks to finish, and digital simulation is fast but doesn't consider analog effects.

Creating behavioral models is only one part of the process of using those models in a mixed-signal verification flow. If the model and implementation do not match, it can damage the entire design process. As a result, there is a need for a methodology to validate the accuracy of a behavioral model automatically against the corresponding design.

Client

LG

Team Size

8

Duration

Dec 2014 to till date

Tools

Cadence IES

Key Responsibilities:

Created TB architecture for AFE MPHY

Extracted top level features

Created a functional coverage document for signoff

Developed a input agent components of RX lane

Coded interface protocol tasks in UVM Driver for RX lane

Developed a efficient monitor to collect the transactions form interface for input agent and output agent

Developed sequences and tests to check the burst data transaction in TX and RX

Developed a scoreboard to check the data integrity

Created top level module to integrate DUT and test bench

Written functional coverage groups based on functional coverage doc

Worked for coverage closure

Project#2: Verified MPHY using UVM – Block level Verification using UVM

Company

Test and Verification Solutions

Designation

Senior Verification Engineer

Project

Developed verification Environment for Analog equivalent behavior model & integrated with digital MPHY verification using UVM

Description

Behavior model is fast and accurate simulation of a full chip with the package. But SPICE can take weeks to finish, and digital simulation is fast but doesn't consider analog effects.

Creating behavioral models is only one part of the process of using those models in a mixed-signal verification flow. If the model and implementation do not match, it can damage the entire design process. As a result, there is a need for a methodology to validate the accuracy of a behavioral model automatically against the corresponding design.

Client

LG

Team Size

8

Duration

Dec 2014 to till date

Tools

Cadence IES

Key Responsibilities:

Created TB architecture for MPHY

Worked for coverage implementation

Extracted top level features

Created a functional coverage document for signoff

Developed a reusable RMMI –TX components

Implemented RMMI – RX Components

Coded interface protocol tasks in UVM Driver in RMMI and DPDN side

Developed a efficient monitor to collect the transactions form interface in RMMI side

Created a monitor to collect the transaction of DPDN side

Developed sequences and tests to check the burst data transaction in TX and RX

Developed a scoreboard to check the data integrity

Created top level module to integrate DUT and test bench

Reported bugs to designer and proposed fix

Written functional coverage groups based on functional coverage doc

Worked for code coverage improvement by writing directed test cases

Project#3: SATA based SSD NAND Flash Controller,16 Flash Channels– SOC Verification using SV

Company

LSI India Research & Development Pvt Ltd

Designation

ASIC DvDS Engineer

Project

Developed verification Environment for SSD Controller for verification using System Verilog

Description

A SSD NAND flash memory controller manages the data stored on flash memory and communicates with a computer or electronic device. Flash memory controllers can be designed for operating in low duty-cycle environments like SD cards, Compact Flash cards, or other similar media for use in digital cameras, PDAs, mobile phones, etc.

Client

Micron

Team Size

12

Duration

July 2013 to Apr 2014

Tools

VCS from Synopsys, Verdi, Viper Magic

Key Responsibilities:

Developed a reusable Verification Environment

Integrated MDIO & JTAG models in to the VE

Developed test cases for AMS & Digital IP’s

Coded checkers for EFUSE model

Verified test cases in RTL & Gate level simulation

Checked connectivity of all DFT modes

Written checkers & Verified intercommunication between IP’s

Coded PLL bring up sequence for System PLL, NAND and DDR PLL’s

Framed error injection test cases

Regression in VCS with all the test cases and verified the reports of simulation

Worked with Validation team for initial test mode setup

Delivered IP mode test case in WGL format to ATE tester

Tested post layout netlist in Zero delay & SDF

Verified DFT logic inserted outside IP’s

Worked for tape out activities

Project#4: SATA based SSD NAND Flash Controller, 8 Flash Channels– SOC Verification using SV

Company

LSI India Research & Development Pvt Ltd

Designation

ASIC DvDS Engineer

Project

Designed DFT modes & Developed verification Environment for SSD Controller for verification using System Verilog

Description

A SSD NAND flash memory controller manages the data stored on flash memory and communicates with a computer or electronic device. Flash memory controllers can be designed for operating in low duty-cycle environments like SD cards, Compact Flash cards, or other similar media for use in digital cameras, PDAs, mobile phones, etc.

Client

Micron

Team Size

12

Duration

Jan 2014 to till date

Tools

VCS, Verdi, Viper Magic

Key Responsibilities:

Designed DFT modes for complete SOC

Integration of SOC pads to IP Wrapper signals

Defined DR & IR control bits for User defined registers

Checked connectivity of all DFT modes

Verified intercommunication between IP’s

Coded PLL bring up sequence for System PLL, NAND and DDR PLL’s

Developed a reusable Verification Environment

Integrated MDIO & JTAG models in to the VE

Developed test cases for AMS & Digital IP’s

Coded checkers for EFUSE model

Verified test cases in RTL & Gate level simulation

Framed error injection test cases

Regression in VCS with all the test cases and verified the reports of simulation

Worked with Validation team for initial test mode setup

Delivered IP mode test case in WGL format to ATE tester

Tested in Zero delay & SDF

Verified DFT logic inserted outside IP’s

Worked for tape out activities

Project#5: IP Verification – RFFE SPI Slave Controller using UVM

Company

Adventura Technologies Pvt Ltd (A Division of Arasan chip systems)

Designation

Verification Engineer

Project

As per customer requirement developed verification Environment for RFFE Slave Controller by using UVM Methodology.

Description

The RFFE Slave IP typically resides in the RFIC in a mobile platform, and utilizes the RFFE bus to identify, program and monitor the registers in RF front end Slave devices through programmed IO. It is designed to support existing standards such as LTE, UMTS, HSPA and EGPRS, and is usable in configurations ranging from single Master/single Slave to multi Master/multi Slave.

Client

EPCOS

Team Size

4

Tools

IRUN from Cadence, VCS from Synopsys, ICCR, IMC

Key Responsibilities:

Developed a reusable Verification Environment

Developed test cases and Sequences

Regression in VCS

Coded assertions as per specifications

Filed bugs with proposing solution for bug fixes

Supported customer queries on verification point

Generated coverage

Improved coverage by writing corner cases

Taken the owner ship of RFFE Master & Slave Verification environment

Project#6: IP Verification – RFFE HOST Controller using UVM

Company

Adventura Technologies Pvt Ltd (A Division of Arasan chip systems)

Designation

Verification Engineer

Project

As per customer requirement developed verification Environment for RFFE Slave Controller by using UVM Methodology.

Description

The RFFE is a 2 wire, serial interface and utilizes 26Mhz clock. The RFFE used to connect RFIC’s of a mobile to their relative front end modules. The commands sequence initiated by RFIC will control slave USID, slave operating state, register write & read to slave registers.

Client

EPCOS

Team Size

4

Tools

IRUN from Cadence, VCS from Synopsys, ICCR, IMC

Key Responsibilities:

Architected & developed the class based verification environment using UVM

Developed a reusable Verification Environment

Developed test cases and Sequences

Verified the RTL module

Regression in VCS

Filed bugs with proposing solution for bug fixes

Supported customer queries on verification point

Generated functional and code coverage for the RTL verification sign-off

Improved coverage by writing corner cases

Coded assertions as per specifications

Filed the bugs with proposing solution for bug fixes

Project#7: IP Verification – UHS2.0 Layer (Ultra High Speed 2.0) using System Verilog

Company

Adventura Technologies Pvt Ltd (A Division of Arasan chip systems)

Designation

Verification Engineer

Project

UHS-II layer was verified using System Verilog & Verilog environment

Description

The UHS-II is a high speed interface up to 312MB/s, Easy implementation for whole system, Compatibility with Legacy SD interface, Ensuring effective performance of data transfer, Low voltage, low power consumption and low EMI.

Client

Intel, Broadcom, Samsung, Apple

Team Size

5

Tools

IRUN from Cadence, VCS from Synopsys, ICCR, IMC, Modelsim

Key Responsibilities:

Developed LINK Layer model using System Verilog and Verilog

Written test cases to test the RTL behavior

Written BFM to support UHS2 packets like CCMD, DCMD, DATA packets transmission

Filed bugs related to Half Duplex, Abort and EBSY Packet

Fired regression runs and generated coverage

Improved coverage by writing corner cases

Written and verified error scenarios

Project#8: IP AB Verification – SD Host Controller 3.0 using OVM

Company

Adventura Technologies Pvt Ltd (A Division of Arasan chip systems)

Designation

Verification Engineer

Project

Verified SD Host Controller 3.0 using OVM environment

Description

The SD Host controller for SDIO, SD memory card, and MMC interface, allows host CPU to access SD and MMC devices. The SD Host is a simple user interface optimized for on-chip bus connection & supports SDIO direct memory access (DMA) operation for high-speed data transfer, SD host controller standard register set

Client

Intel, Broadcom, Samsung, Apple

Team Size

12

Tools

IRUN from Cadence, VCS from Synopsys, ICCR, IMC, Modelsim

Key Responsibilities:

Test cases were written to test the SD Host functionality

Added assertions in the Functional Coverage module

Filed Bugs in Bugzilla

Fired regression runs and generated coverage

Improved coverage by writing corner cases

Written and verified error scenarios

Support Customer queries on verification point after release to the customer

Project#9: DUAL PORT RAM Verification using System Verilog

Project

Designed in Verilog HDL and verified Dual Port RAM using System Verilog

Description

Dual-ported RAM (DPRAM) is a type of Random Access Memory that allows multiple reads or writes to occur at the same time, or nearly the same time, unlike single-ported RAM which only allows one access at a time.

Team Size

1

Tools

Xilinx ISE, Modelsim

Key Responsibilities:

Implemented the Dual Port Ram using Verilog HDL independently

Architected the class based verification environment using System Verilog

Verified the RTL module using System Verilog

Test cases were written to test the functionality

Generated functional and code coverage for the RTL verification sign-off

Achievement:

Received the best performer award from Adventura Technologies for the 1st quarter of 2012

Received gold medal from district educational officer for securing Mandal 1st in SSC Board Exam In year 2003

Catch the spark award for individual contribution for SOC Verification in LSI India Research & Development Pvt Ltd

Personal Details:

Father’s Name : Adikesavula Naidu G

Date of Birth : 15/07/1988

Gender : Male

Nationality : Indian

Marital Status : Single

Languages Known : English, Telugu, and Kannada.

Pan Number : AKVPT3303J

Passport Number : K8254456

Permanent Address : C-25, Korlamitta,

Puthalapattu,

Chittoor, A.P – 517124.

Declaration

I hereby declare that the above written particulars are true to the best of my knowledge and belief.

Date:

Place: Bangalore (Thyagarajula Naidu)

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