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BE/Electronics & Communication/76.2 % Agg/2014 Passed out

Location:
Bengaluru, KA, India
Posted:
July 07, 2015

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Resume:

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CHAITHRA S ANCHATGERI

Address: #***/*, ***** *****

Maruthi Nagar, BEML Nagar post Mobile: +91-886******* Karnataka India Email: acqmje@r.postjobfree.com

Objective

A position as the Entry level Engineer, which demands me to work with highly technical software or hardware applications.

Educational Qualification’s

Degree/

Certificate

Institution Board/

University

Year of

passing

Percentage

B.E

(Electronics and

communication)

Dr.T.Thimmaiah Institute

of Technology,

KGF

Visvesvaraya

Technological

University, Belgaum

2014 78%

XII

BEML Composite Pre

University College,

BEML Nagar KGF

Pre University

Board,

Bangalore

2010 82%

X BEML Composite Junior

College, BEML Nagar

KGF

Karnataka Secondary

Education Board,

Bangalore

2008 90%

Technical Skills

Software Skills Microsoft Word, Power point and Excel. Programming skills C, HDL Verilog, Assembly (8086) CAD Tools Cadence Virtuoso ADE, Xilinx v10.1, ModelSim v6.3f, Matlab R2008B, Masm.

Operating systems Windows XP/Vista/8.

Subjectof interest Logic Design, Microprocessors, CMOS-VLSI, Computer Networks, Operating systems.

Page 2 of 2

Project Undertaken

“Design of ‘Switched Inverter Scheme (SIS) Flash ADC’ for low power and high speed Applications”

CAD Tool : Cadence Virtuoso ADE (90nm Technology), SpectreSimulator.

Team : 4 Members

Duration : 5 Months (January - May 2014)

Description: The project is aimed to design a high speed low power SIS flash ADC by using CMOS inverter as a comparator rather than using analog comparator. In analog comparator, conventional method of using resistor ladder network is utilized for externally generating the reference voltage. Whereas in the SIS comparator reference voltage is set internally by adjusting the threshold voltage of each voltage comparator by separately sizing the length and width (aspect ratio) of each transistor. Thus the SIS design eliminates the Resistor Ladder Network and optimizes area, power and power delay product (PDP). Power dissipation is reduced to 10.44mW. Delay is reduced to 81nS. Achievements

Stood among the top 15% in Common Entrance Test held by Karnataka Examination Authority in 2010

Secured 2nd place in “Group singing” conducted by Dr TTIT in 2013.

Participated in zonal levels of ROBOTRYST-2013 organized by ‘Robosapiens Technologies Pvt.Ltd’.

Participated in inter college CLIMATE CHANGE QUIZ-2013 held at ‘IISC’, Bangalore.

Participated actively in various competitions during college fest. Hobbies and Interests

Reading News papers “The Hindu”, “Prajavani” and looking forward to publish article in Open space column.

Playing basket ball, Chess and Shuttle Badminton.

Networking on Facebook and LinkedIn.

Personal Details

Date of Birth 04-01-1993

Father’s Name Shivalingappa V Anchatgeri

Languages Known Kannada, English, Tamil, Telugu and Hindi Email secondary acqmje@r.postjobfree.com

Permanent Address #172/B, Akash Nivas, Maruthi Nagar Kathalli BEML Nagar post KGF. Pin 563115 India



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