Yunhui Zeng

*** ******* **

San Francisco, CA ***32

469-***-**** Cell

acqlh1@r.postjobfree.com

OBJECTIVE: To obtain a full time job in the field of computer science&engineering EDUCATION: Southern Methodist University(SMU), Dallas, TX GPA:3.52 Master of Science in Computer Engineering, May 2015 Beijing Info Sci & Tech University(BISTU), Beijing, China GPA: 3.22 Bachelor of Engineering in Communication Engineering, July 2013 SKILLS: Programming Languages: C, Python, Assembly language, Verilog HDL Operating System: Windows, Mac, Linux;

Software: Xilinx, Quartus, Matlab, Cadence, Keli uVision Related courses: Digital System Design, Found/Formal Verification&Validation, Micro-controller

Architecture&Interface, Testing of VLSI Circuits

Multilingual: English, Chinese

PROJECTS: Sequential Circuit Reachability Analysis implement with CUDD Spring 2014

• Presented a method for sequential reachability analysis with the CUDD(Colorado University Decision Diagram) package and parse net lists files in ISCAS89 circuit format

• Implemented a program to build the monolithic Transition Relation BDD and per- form the image computation with C language

• Used dynamic variable reordering for the BDD to find out the difference in total number of reachable states, the number of iteration, and actual data computation, etc.

Weighted Random Test Patterns in Build in Self Test Fall 2014

• Generated weighted random test patterns by LFSR(Linear Feedback Shift Register) hardware circuit in Quartus implemented with Veriog HDL

• Wrote test bench file for the CUT in Cadence Simvision to obtain the simulation files

• Test the value of inputs and outputs in the Tessent Software to gain the fault cover- age and analysis them

ARM MCBSTM32C Finite State Machine with timers and interrupt Spring 2014

• Create a finite state machine to control a toy car’s servomotor and the 08 LEDs using the ARM board.

• Implemented uVision/ARM development tools, use the Assembly Instruction and C language to build the finite state machine, The state machine uses a combination of timers loops and interrupts.

• Compared the behavior between polling, interrupt and timer. Senior Design

Fall 2013

• Created DDS (Direct Digital Synthesizer)on Xilinx ISE Design Suite 12.2_2 on Xilinx Spartan-6, used the ModleSim to simulate the result

• Implemented the DDS module based on Verily HDL, design the

• Generate sine-wave as the output, frequency range is 0Hz-10MHz