ANUSUYA DEVI S

No-*/***, Min Nagar, Ariyalur District, Tamilnadu, INDIA

Contact : +919********* ; Email : acqkzx@r.postjobfree.com PROFILE SUMMARY

Self motivated Science Graduate keen and interested to undertake research and aiming to contribute effectively and efficiently, through the utilization of my knowledge, talent and skills, to the organization in specific and the society as a whole

Hands-on experience on Physical verification for various design using cadence tools in 180nm technology and Cadence virtuoso schematic editor,analog design environment.

Gained significant exposure in VLSI Systems.

Accented with the latest trends and techniques of the field, completed M.E in VLSI Design from R.M.K Engineering College, Kavaraipettai with CGPA 8.3.

Successfully completed academic projects on A 9 Bit Pipelined Time To Digital Converter Using Time Register.

Conceptually strong with an innovative and analytical approach to the work with an eye for detail. Enriched with the ability to learn new concepts & technology within a short span of time.

Self-motivated, hardworking and goal-oriented with a high degree of flexibility, creativity, resourcefulness, commitment and optimism.

Technical Skills

Programming language : Java, Verilog HDL, Spice.

ASIC Design Tools : Cadence Virtuoso schematic editor, analog design environment Functional Verification Tools : ModelSim

Synthesis Tools : Xilinx ISE, Altera Quartus II

Hardware Implementation : Spartan 3, 3E and Vertex 6 FPGA boards. Analog Simulation : Hspice

PROJECT WORK

Design and Implementation of a 9 Bit Pipelined Time To Digital Converter Using Time Register

Tools Used : Cadence Virtuoso schematic editor, analog design environment Technology Used : gpdk 180nm

Analysis : Transient, Power analysis

Description : The aim of the project is to increase the speed of conversion and to increase the dynamic range. For this, pipelined operation is and time-register is used to store time information with a clock signal. Along with a pulse train time amplifier, a 2.5 bit pipeline stage and a 3 bit delay line stage is implemented in 180 nm CMOS process achieves dynamic range of 1760ps per stage.

Design and Implementation of FPGA Based Channelizer With Power Optimization For Software Defined Radio

Tools used : Xilinx ISE

Description : Multiple communication channel supports RF transmission, such as that in a Software Defined Radio (SDR) warrants the use of channelizer to extract required channel from the received RF frequency band. It applies to low power and high efficiency applications in wireless and satellite communications (SATCOM) domains. FPGA based technology provide much lower Non-Recurring Engineering (NRE) which makes programmable channel solution

AREA OF INTEREST

VLSI Design Techniques.

Digital System Design.

PUBLICATIONS

S.Anusuya Devi, P.Latha “Design and Implementation of A 9 Bit Pipelined Time to Digital Converter Using Time Register” (International Conference on Advance Research in Technology and Engineering-2015) EDUCATION

Degree: M.E. (VLSI Design) R.M.K Engineering College, Kavarapettai. 83.3 Degree: B.E. (Electronics and

communication Engineering)

Anna University, Tiruchirappalli. 83.1

Class XII : Matric SRV Girls Higher Secondary School, Rasipuram.

92.5

Class X: CBSE Aditya Birla Public School, Reddipalayam. 85.8 ACADEMIC ACHIEVEMENTS & CO-CURRICULAR ACTIVITIES

Presented Paper International Conference on Advance Research in Technology and Engineering

Attended a workshop on CYBER SECURITY in Anna University Chennai.

Attended a workshop on Android in PSG College of Engineering Coimbatore.

Underwent In – Plant Training for 5 days in BSNL in Trichy.

Underwent Industrial Visit to ISRO in Kerala.

PERSONAL DETAILS

Nationality : Indian

Marital Status : Single

Date of Birth : 05

th

August 1991

Father’s Name : Selvarasu.K

Sex : Female

Linguistic Proficiency : English, Tamil

I hereby declare that all the details furnished above are true and correct to the best of my knowledge and belief.

Anusuya Devi.S

Contact this candidate