SACHIN

Email : acqkwp@r.postjobfree.com

Mobile: +91-974*******

OBJECTIVE

To grab an opportunity and set myself a goal where I can be innovative and attain a challenging position by exercising my interpersonal and professional skills to the fullest for the growth of the organization and mine as well.

QUALIFICATION

Degree : M.Tech in VLSI Design and Embedded Systems.

University : Visvesvaraya Technological University, Belgaum.

College : BMS college of Engineering, Bangaluru.

ACADEMIC DETAILS

Degree/

Certificate

Institution

Board/university

Percentage M.TECH

(VLSI & ES)

BMSCE

Bangaluru

VTU

Belagum

77.88

(upto 1st sem)

B.E(ECE)

(2014)

Dr.A.I.T

Bangaluru

VTU

Belgaum

81.30

12th

(2010)

Best PU college

Of Bellary

PUC

Karnataka

82.50

10th

(2008)

Sri.J.B.K High school of B.kalyan

SSLC

Karnataka

77.92

INTERESTED SUBJECTS

CMOS VLSI Design, Digital Logic design

Basics of ARM processor and embedded systems

Known programming languages C and Verilog

TECHINICAL SKILLS

Good program skill in verilog coding.

Familiar with Cadence, Xilinx tools.

We did Project on “Edge Detection Technique for image segmentation using ACO approach”.

ACADEMIC PROJECT PROFILE

Title: Basic gates operations using CMOS and FINFET technology of 32nm in SPICE tool.

Project description:

In cmos circuits by varying the width and length of the gate it can be seen that the static and dynamic responses obtained are too large. The gate length can be decreased to get a better response for a given cmos circuit therefore the gate length was decreased from 180nm to 120nm and then to 70nm and to so on till 32nm, but the length of the gate cannot be decreased below that since the gate becomes so less in length and the source and drain of a cmos will be shorted. In order to overcome this problem we introduce FINFET technology.

CO CURRICULAR

Attended workshop on “ FPGA Digital Design Lab “conducted by VTU Extension centre”.

Volunteered and Participated in the event “ National Confernce on networking, embedded and wireless systems”.

Attended workshop on “schematic and layout design in 45nm technology” held at Bmsce

PERSONAL PROFILE

D.O.B : 04-03-1993

Father name : Chandrasekhar Patil

Languages known : English, Kannada & Hindi.

Hobbies : Playing as well watching cricket, listening to music.

Address : Sale-Beernalli

Tq-Chincholi

Dis-Gulbarga, Karnataka -585306

PERSONAL ABILITIES

Willingness to learn

Team facilitator

Hard worker

Ability to work in a group or alone

DECLARATION

I, hereby say that above information is correct to the best of my knowledge. If given an opportunity, I will prove to be faithful for your estimated organization.

Sachin

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