M DEEPA

Career Objective:

To become a reputed professional and apply my skills to serve the organization and help it to meet it’s ever growing demands, so as to have a very successful and distinguished career.

Education:

Graduation:

Course : M.E. – VLSI Design

Institution : Dr.Sivanthi Aditanar College of Engineering, Tiruchendur

Year of passing : 2014

Percentage obtained : 81.00%

Course : B.E. – Electronics & Communication Engineering

Institution : Infant Jesus College of Engineering, Tuticorin

Year of passing : 2012

Percentage obtained : 78.10%

Higher Secondary:

School : St. Ignatius Convent Higher Secondary School, Palayamkottai

Year of passing : 2008

Percentage obtained : 80.83%

Secondary:

School : St. Ignatius Convent Higher Secondary School, Palayamkottai

Year of passing : 2006

Percentage obtained : 86.20%

Computer Proficiency:

Operating Systems : Windows, Linux

Programming Languages : C, C++,

Program Simulators : Xilinx ISE, Model Sim, MATLAB

Electronic Design Automation : Cadence, Tanner, Microwind

Areas of Specialization:

VLSI Design

Digital Electronics

Linear Integrated Circuits

Inplant Training:

Have successfully undergone Inplant Training at High Power Television Transmitter in Tirunelveli for 1 week.

Academic Projects:

Done the final semester UG project in the area of Embedded Systems under the topic “Web based cell phone tower fault telemetry system” with the sole aim of solving the faults in cell phone towers through web by using embedded system.

Done the PG project in the area of Low Power VLSI Design under the topic “Design of Modified Dynamic Regenerative Comparator for Power and Delay Reduction” with the aim of increasing speed and minimizing the power and area in comparator.

International Conferences:

International Conference Paper Title

Institution

Date

Design of Modified Dynamic Regenerative Comparator for Power and Relay Reduction

Sethu Institute of Technology, Virudhunagar.

28th March 2014.

National Conferences:

National Conference

Paper Title

Institution

Date

Web based Cell Phone Tower fault Telemetry System

The Rajaas Engineering College, Tirunelveli.

15th March 2012-16th March 2012.

Workshops:

Workshop Title

Institution

Date

Modeling, Simulation and Synthesis of VLSI using CADENCE

K.Ramakrishnan College of Engineering, Trichy.

21st February 2014.

Analysis and Design of Analog Integrated Circuits

Thiyagarajar College of Engineering, Madurai.

9th May 2013-10th May 2013.

Two Days Hands-on Training Programme on IC System Design using Mentor Graphics EDA Tool

Anna University Regional Centre, Coimbatore.

18th April 2013-19th April 2013.

Self-Balancing Bot Workshop

Kurukshetra 2012, College of Engineering, Guindy, Chennai.

30th January 2012-31st January 2012.

Personal Details:

Date of Birth : 10.01.1991

Sex : Female

Nationality : Indian

Languages known : Tamil, English

Father’s Name : G.Murugan

Permanent Address : 941-D, 8th Street, Meenakshi Nagar,

TVS Nagar,

Tirunelveli - 627 011.

References:

M.Manicka Raja, Assistant Professor, Department of Computer Science and Engineering,

SCAD Institute of Technology, Tirupur. Mobile: 962-***-****

Dr.A.Beno, Assistant Professor, Department of Electronics and Communication Engineering, Dr.Sivanthi Aditanar College of Engineering, Tiruchendur. Mobile: 944-***-****

Declaration:

I declare that all the particulars stated above are correct and true to the best of my knowledge and belief.

Place :

Date : ( M DEEPA )

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