CURRICULUM VITAE

CAREER OBJECTIVE :

Intend to build a career with leading corporate of hi-tech environment with committed & dedicated people, which will help me to explore myself fully and realize my potential. Willing to work as a key player in challenging & creative environment.

EXPERIENCE:

Currently In CAREER POINT UNIVERSITY, KOTA from July, 2014.

Have been worked as a lecturer in Electronics & Communication in MAIIT, KOTA from July,2010 to Feb., 2014..

EDUCATION QUALIFICATION :

M.T.ech Scholar (Result Awaited) in VLSI DESIGN from Poornima College Of Engineering, Jaipur affiliated by RAJASTHAN TECHNICAL UNIVERSITY, KOTA.

B.E. with 70.03% HONOURS in Elec. & Comm. From Modi Institute Of Technology, KOTA affiliated by RAJASTHAN UNIVERSITY, JAIPUR in 2009.

Senior Secondary (RBSC, Ajmer) With 71.54% in 2005.

Secondary (RBSC, Ajmer) With 78.67% in 2003.

TECHNICAL SKILLS:

Electronics & Others

EDC, Digital Electronics, DSP, VLSI, AE

Designing Skills

VHDL, ESD

E.C.A.:

Organized an 6-days Educational Tour of 84 students of Electrical & Electronics Branch at Delhi-Haridwar-Mussoorie-Rishikesh in March, 2015.

Organized National Seminar on “Importance of Power Electronics” May 2015, Career Point University, Kota(Rajasthan).

CONFERENCES/WORKSHOPS:-

Published paper in International Journal Of Advanced Technology & Engineering Research(IJATER Journal), Volume 2, Issue 3, May 2012, ISSN NO. 2250-3536 paper entitled “VHDL Implementation Reversible Logic Gates.”

Presented paper in International Conference on “4-Bit Reversible Full Adder Using DKG Gate Implementation in VHDL” April 2012, organised by Janardan Rai Nagar Rajasthan Vidyapeeth (D) University Udaipur.

Presented paper in National Conference on “Reversible Full Adder Gate using

Nano-technology” April 2012, organized by Modern Institute Of Technology &

Research Centre Alwar.

Attended one day Workshop on “Research Methodology” February 29,2012 organized by Departments of Computer Engineering, Poornima College of Engineering, Jaipur. In Association with Institution of Engineers, India.

Attended one day IEEE Workshop on “Knowledge Mining and Their Models” Saturday December 24th 2011, organized by Departments of Computer Engineering and Information Technology, Poornima College of Engineering, Jaipur.

National Workshop on “MATLAB and SIMULINK (WMS-2013)”, June 2013, organized by School of Electrical, Electronics & Communication (SEEC) Engineering,MANIPAL UNIVERSITY JAIPUR(RAJ.).

Present a paper “Review Paper on FPGA Implementation of Adaptive Filtering Algorithms”, in IPASJ International Journal of Electronics & Communication (IIJEC), ISSN2321-5984, Vol. 2, issue 9, September 2014.

Present a paper “Area Efficient FPGA Model of LMS Filtering Algorithm”, in Springer International Conference on Recent Cognizance in Wireless Communication & Image Processing (ICRCWIP-2014), January-2015 in under press.

M.Tech. PROJECT:

Project Name : An Area Efficient FPGA Design of Adaptive Filtering Algorithm Using VHDL.

Description : Design LMS and NLMS Adaptive Filtering Algorithm Using VHDL & then compare their area occupied.

B.E. PROJECT:

Project Name : “ MAGLEVE TRAIN ”

Description : Maglev Train is a new vehicle without support wheel and baised on principle of magnetic levitation

TRAINING DETAILS:

Year

Duration

Industry

Field

2007

30

DRM Office Kota.

Rail Net, Data Logger

2008

45

VEDANT INST., LUCKNOW

VLSI, ESD

Projecting Skills :

’64 BIT ALU’ Completed In VLSI (VHDL)

‘METRO TRAIN’ Completed In (ESD Based).

‘Traffic Light Control system’ (Embedded System Design Based).

‘Traffic Light Control system’ In (VHDL)

’Temperature Controlled Fan’ in EC Domain In “ABHIVYAKTI-2007” Held In ECK,KOTA -Done in B.E.IV Sem

Designing SOFTWARE In SOFTEMPORE In “NUCLEUS”

Name : Mr. Devendra Goyal

Father’s Name : Mr. Ramesh Chand Goyal

Date of Birth : Sep.8, 1987

Languages Known : English, Hindi

Nationality : Indian

Sex : Male

Permanent Address : S/O Ramesh Chand Goyal

Opp. Paliwal Compound, 542, Chhawani Kota, Rajasthan. Pin Code -324007

Ph. No. 074*-*******, 946*******

DECLARATION :

I consider myself familiar with Electronics & Communication Engineering Aspects. I am also confident of my ability to work in a team.

I hereby declare that the information furnished above is true to the best of my knowledge

Date:

Place: KOTA (DEVENDRA GOYAL)

Contact this candidate