SACHIN RAJ AGGARWAL

ASIC/FPGA ENGINEER with *.* yrs exp. at TRANSWITCH / SOLARFLARE;

M.Tech. (VLSI Design) from C-DAC, Noida

Contact Phone

Mobile - +91-928*******

+91-925*******

e-mail Id - acqjyd@r.postjobfree.com

acqjyd@r.postjobfree.com

Aspiring to pursue assignments in the domain of Semiconductor & Electronics engineering with a growth oriented organization of repute and to Explore VLSI Design – SOC/IP ASIC Design & Verification

Career Profile

>2.5+yrs. SoC/IP RTL Verification Engineer for FPGA/SOC project based on UVM and using System Verilog Test benches, UVM/VMM methodologies, RTL Coding & standard protocols as I2C, SPI

Strong Knowledge on – ARM, AHB/AXI, Ethernet, CPU, Graphics (DDR)

Projects Undertaken on SOC/IP Verification (2 projects)–

MEMORY CONTROLLER TOP LEVEL verification having sub-blocks - Real MIPS, SPI

Controller, Flash Memory and AES, CMAC blocks for data security;

QUAD SPI verification IP using UVM methodology; Verification IP of I2C Slave in UVM

& System Verilog; Triton (HDMI Port) etc

Enough experience in Waveform analysis & understand DUT issued besides interpersonal problem solving skills, Test Planning, Test Case Identification, parallel regression, Functional & Code coverage analysis

Expertise in Verilog, System Verilog and sound in VHDL & OOPS

Proficiency in scripting language - Perl, C++

Expertise in concepts Code coverage with features in existing simulators

Capable of developing ‘C’ tests – created test cases in C for Project MC Top Level project.

Worked on SOC/IP level verification passing test cases, test benches, Building environment using System Verilog & OVM/UVM Methodology

Knowledge of Functional coverage using HVL language features and assertions.

Independent and able to deliver assigned tasks within time

Worked on Backend projects i.e. - Single Bit Dual Port SRAM Cell Design and on Frontend projects i.e. AMBA AHB bus interface, Timer, FIFO.

M. Tech. (VLSI Design) 2011-13 & B. Tech. (Electronics & Comm. Eng.) 2006-10

Adaptable and a quick learner; possesses skills to work under pressure.

Possess strong management, communication & interpersonal skills.

Technical Skills / IT forte

HDLs / HVL

SystemVerilog, Verilog, VHDL

METHODOLOGY

UVM; VMM & OVM

Scripting Languages

Perl, Tcl

VLSI/EDA TOOLS (FRONTEND)

Vcs (Synopsys), Model Sim (Mentor Graphics), Questa (Cadence),

VLSI / EDA TOOLS (BACKEND)

Tanner EDA Tools, IC Station(Schematic, Layout Editor, LVS, DRV, SDL), Matlab

Operating Systems

Linux(CentOS-5.2), Unix (basic), Windows XP/ 2000

Standard Protocols

I2C, SPI OTHER SKILLS- C/C++, RTL CODING

Work Experience (3+yrs.)

Designation

Organization

Duties

Joining Date

Remark

Engineer Verification

Solarflare Pvt Ltd (previously known as Transwitch), New Delhi

ASIC/SOC/IP Verification

10.03.2013

to date

System Verilog, OVM/UVM/VMM

Graduate Engineer Tr.

Incise Infotech Noida

VLSI Designing

Aug.,10-July,11

VLSI, Verilog, EDA Tools

Technical Trainer

Cetpa Infotech Noida

train students in C/C++

June,10-July,10

@ Rs.10,000/-p.m.

Academics

Gate qualified (Gate examination 2011 qualified)

YEAR OF PASSING

GATE SCORE

GATE PERCENTILE

ALL INDIA RANK

2011

456

94.80

7126

EDUCATIONAL QUALIFICATIONS -

Degree (University/Board)

Period

Institute

Percentage

M. Tech. (VLSI) GGSIPU, Delhi

2011-13

C-DAC, NOIDA

75.63%

B. Tech. (ECE) GGSIPU, Delhi

2006-10

HMRITM, Delhi

70.48 %

XII (under 10+2 ) CBSE

2004-05

SBKV Sr. Sec. School

85.6 %

X (under 10+2) CBSE

2002-03

SBKV Sr. Sec. School

65.8 %

Projects Handled Currently (with Transwitch / Solarflare) -

Title (Project – 1)

Memory Controller Top level verification having sub-blocks - Real MIPS, SPI Controller, Flash Memory and AES (Advance Encryption Standard), CMAC (Cipher based Message Authentication Code) blocks for data security

Used – Tools/skills

Vcs (Synopsys) SystemsVerilog UVM Methodology

Testbench OVM Methodology Flash Memory

Title (Project – 2)

Quad SPI verification IP (using UVM)

(verification using Flash Memory & IMEM for DMA purpose)

Used – Tools/skills

Vcs (Synopsys) SystemsVerilog UVM Methodology

Testbench Linux Flash Memory

Title (Project – 3)

Verification IP of I2C Slave in UVM & System Verilog etc

Used – Tools/skills

Vcs (Synopsys) SystemsVerilog UVM Methodology

Testbench Linux

Title (Project – 4)

Triton (HDMI Port) – running regression & analyzing reports

Thesis/Projects

M. Tech MAJOR Project

Title

Design of Serial Peripheral Interface (SPI) Slave for C-DAC, Noida

Used - Tools /

Operating Sys.

Modelsim (Mentor Graphics) Verilog

RTL coding, testbench Linux / Windows

Project Description

The Direct Memory Access (DMA) allows accessing of system memory for reading and writing purposes without any intervention of CPU/Processor. Implemented Features: Pipelining technique has been introduced between DMA & SPI Simulation written for the DMA SPI Interface system Waveforms generated and analyzed.

Title

Single Bit Dual Port SRAM Cell Design for C-DAC, Noida

Used - Tools /

Operating Sys.

IC Station (Mentor Graphics) LVS, Schematic

Layout Editor Linux / Windows

Project Description

1-bit Dual Port SRAM Cell designed & developed along its - Sizing, Optimization, Delay Analysis, Layout creation for 8T SRAM Cell, LVS, DRV Check, RC extraction. Implemented Features: Area efficient Low Power Consumption Can be configured up to Transistor Level.

B. Tech Major Project for GGSIP University

Title (Project - 1)

Infra Red Based Obstacle Avoiding Robot

Language/Skills

C, C++; Embedded System; using 8051 Microcontroller; IR trans-receiver; & used – u-vision Keil for coding.

Title (Project - 2)

Lead Acid Battery Charger With Voltage Analyzer

Title (Project - 3)

Electronic Alarm Clock using Verilog with HP

Awards & Recognitions

In Professional Field -

Achieved “quick learner and fast ramp” recognition from wherever I have worked.

Attended workshop on Semiconductor EDA Tools by Cadence at Park, New Delhi

Attended Advanced Analog & RF workshop by IEEE at ST Microelectronics, Gr. Noida.

Got appraisals & accolades from Management & Students while training them.

In Academic Field -

Won IInd Prize in School XIIth class with 4 distinctions and 2 above 90% marks.

Won Certificate of merit from class I, class VII, VIII and XII during schooling.

In other Field -

Been excellent & active chess player during schooling & won many prizes and certificates including Sub-Junior Championship, Inter School Championship, and Open Rating Championship etc.

Represented college for chess in Intra College Sports Competition of GGSIP University 2007, 2008. 2009 & 2010 and won 2nd & 3rd Prizes

Personal Details

Gender

MALE

Marital Status

Single

Date of Birth

26.10.1987

Nationality

Indian

Father’s Name

RAJESH AGGARWAL

Mother’s Name

PRABHA AGGARWAL

Hobbies

Playing Chess – my most favorite hobby specially blitz

Online Games – playing all kinds of action & puzzle games

Watching Movies – to watch action, comedy & thrillers

Listening Music – to all kinds of music

Strength

Simple & Sober Adaptable

Skilled to work under pressure Sincere & Honest

Strong Managerial & Interpersonal Skills Quick learner

Contact Address

H.No.- 3 / 72, 3rd Floor, Nirankari Colony, Delhi – 110009. India

I hereby declare that the above mentioned information is correct up to best of my knowledge and I bear the responsibility for the correctness of above mentioned particulars.

(Sachin Raj Aggarwal)

Date : 25th June, 2015 Ph. (mobile): 928-***-**** - 925*******

Place : New Delhi (India) e-mail id – acqjyd@r.postjobfree.com

acqjyd@r.postjobfree.com

Contact this candidate