AKHTAR RAAZ www.linkedin.com/in/akhtarraaz/

**** **** ****** ******, *** 109, Tempe, Arizona 85281, acqjl0@r.postjobfree.com, 480-***-**** OBJECTIVE: Actively seeking full time opportunities in Analog/RF/Mixed Signal and Application Engineering domain. EDUCATION

● Master of Science, Electrical Engineering GPA: 3.05/4.00 Ira A. Fulton School of Engineering, Arizona State University August 2013-May 2015

● Bachelor of Technology, Electronics and Communication Engineering GPA: 7.96/10.00 Future Institute of Engineer and Management August 2007-June 2011 KEY SKILLS

● Design/Simulation Tools: Cadence ICFB, Virtuoso, Spectre, ADE, ADS,, Ledit, Pspice, Labview, Simulink, Hspice

● Programming Tools/Languages: Verilog-A, C/C++, Matlab, Perl

● Lab Equipment: Signal Measurement, Signal Generator, Phosphor Oscilloscope, Vector Signal Analyzer, Sourcemeter

● Relevant Courses: Communication Transceiver Circuit Design, High Speed I/O Circuits, Oversampling Σ Converters, Analog Integrated Circuits, Adv. Analog Integrated Circuits, VLSI Design, Digital System Circuits, CMOS Device Fabrication WORK EXPERIENCE

● Analog Mixed Signal Design Intern- TE Connectivity Summer'14, ASU, Supervisor: Phil McClay

-Developed data acquisition routines (Installer and application file) for various RF test equipment in LabVIEW. Developed VI models for AGILENT 8563 and E3610, KEITHLEY 2400, TEKTRONIX TDS3032 and Oscilloscope.

-Achieved precision for H-S MXP 1x8 connectors, long and medium cables by analyzing S21 parameters. Implemented R&R (repeatability and reproducibility) measurement system analysis.

● System Engineer, Unit-RCL Infosys Limited, Bhubaneswar, October 2011-August 2013

-Provided application support, bug fixing and maintenance support for coded batch job activities for EDI messages transaction, for American President Lines (APL). Used Mainframe and REXX programming tool. ACEDAMIC PROJECTS

● Fixed Frequency PLL Design For High Speed SATA Interface Instructor: Dr. Hongjiang Song, Fall'14 ASU

-Designed a fixed frequency 4-phase PLL targeted at data recovery for a 3.2 Gbps high-speed I/O circuit (SATA 3G) in TSMC 0.18 um process with 100 MHz reference clock and 5uA on chip current design constraints. Achieved output clock frequency of 1.6 GHz, peak-peak jitter of 2.561 ps and phase spacing error <0.4 o

-PLL design included transistor level implementation of a phase frequency detector circuit, a charged pump, VCO and frequency divider circuit. Implemented the behavioral models using Verilog-A coding techniques.

● Second Order CT Σ Modulator Design And Simulation Instructor: Prof. Douglas Garrity, Fall'14 ASU

-Designed a single loop low-pass Σ modulator using Matlab delta sigma toolbox for low voltage applications in a GSM radio receiver. Used CIFB architecture. Verified the operation by implementing a simulink model of the modulator. Achieved better SNR (98 dB) and stability for bandwidth of 100 KHz optimizing position of poles and zeros.

-Designed a spectre macro model of the fully differential second order continuous-time Σ modulator. Achieved specifications- SNR>74 dB, BW: 500 KHz. Designed the quantizer block using 15 comparators. Current DAC was used.

● OTA and Folded Cascoded Amplifier Design Instructor: Prof. Bertan Bakkaloglu, Spring'14 ASU

-Designed a symmetric enhanced output impedance OTA (Operational Transconductance Amplifier). Designed layout for the OTA implementing common centroid topology in TSMC 0.3 um process, with DRC and LVS match.

-Designed single ended PMOS input folded cascoded amplifier with a class AB output buffer circuit in order to operate with low resistive load. Achieved 1st order system implementing pole splitting techniques using compensation capacitor of 240 fF to ensure better stability.

● Ultra Wideband LNA Design For Different Wireless Standards Instructor: Prof. Jennifer Kitchen, Spring'14 ASU

-Designed an Ultra Wideband low NF LNA using IBM7RF process to cover wide band of operation (3-10GHz) for radios with different wireless standards. Achieved specifications- S11, S22<-10 dB, NF<5dB, S21>18 dB (flat band), low power, better reverse isolation implementing current reuse technology, cascoded structure and shunt-series peaking technique.

-Designed layout for a common source inductively degenerated LNA using IBM7RF process, with DRC clean and LVS match. Performed post layout schematic analysis for all S-parameters.

● Low Dropout(LDO) Voltage Regulator Design Instructor: Prof. Jennifer Kitchen, Fall'13 ASU

-Designed a stable LDO system with BW>100 KHz and PM=60 DEG implementing pole-zero compensation technique using compensation circuit with zero nulling resistor. Achieved design goals of conversion of 2.5 V input to a regulated 2.25 V output for design constraints- 50mA on chip current with less than 5% ripple.

● 32 bit MIPS Processor and RF Cell Design Instructor: Prof. Lawrence Clark, Spring'14 ASU

-Completed RTL to GDSII format for 32-bit multi-cycle MIPS processor using TSMC 0.3 um process involving synthesis, floor planning, verification, pre-CTS, clock tree synthesis, post-CTS, buffer implementation, nano route, timing analysis. Implemented RC compiler to perform synthesis. Performed post layout STA using synopsis Primetime tool.

-Designed a 16x32 Register file with two static read and one write port using transmission gates and the entire layout for 32 bit in cadence6. Wrote Hspice programming to generate netlist used to analyze functionality of the RF cell for all process corners. Optimized the design layout area and load capacitance implementing diffusion sharing techniques. RESEARCH PUBLICATION

● Microstrip Antenna with Centrally Loaded Inductive Discontinuity for Dual Band Operation Published in: ICACC, issue- March 2013 ACCENTS, Ranchi-India, Nov 2012-Mar 2013