Page * of *

ADITYA SUNIL GOKHALE

***, ******* *****,

Plot no. 162, MCCH society,

Panvel-410206, Maharashtra

India

Contact No.: +919*********

Email id: - acqjhw@r.postjobfree.com

Objective

To secure challenging opportunity to improve myself as a best professional in VLSI field

(design/verification).

VLSI Domain Skills

HDL : Verilog

EDA tools : ModelSim, Xilinx ISE 14.7, HSPICE 2008.03, Cadence Virtuoso & encounter (basic), Tanner EDA v13.0

Knowledge: RTL Coding, VLSI design flow, ASIC flow, CMOS concepts. Professional Qualifications

Completed final year project from CDAC ACTS, Pune.

M.Tech. in VLSI Design from “Vel Tech Dr. RR & Dr. SR Technical University, Chennai” in 2015 with CGPA 7.59.

B.E. in Electronics and Telecommunications from “Vidyalankar Institute of Technology, Mumbai” affiliated to the University of Mumbai in 2012 with aggregate 59.38%.

HSC from “Mahatma junior college of Arts, Science and Commerce, New Panvel”

(Maharashtra state board) in 2008 with 80.33%

SSC from “Adyakrantiveer Vasudev Balwant Phadke vidyalaya, New Panvel”

(Maharashtra state board) in 2006 with 86.40%

Academic Projects

Title: Ternary Analog to digital converter using Carbon nanotube field effect transistor Coding: SPICE

EDA tool: HSPICE v2008.03

Duration: September 2014-May 2015

Company: CDAC ACTS, Pune

Description: In this, ADC makes use of ternary logic & CNTFET. Main aim of the project was to reduce area and improve accuracy of A/D converter. In this reduction in area was achieved by means of both ternary logic & CNTFET as ternary logic reduces the no. of interconnects and CNTFET facilitates the lowering of feature size below 20nm. Also Ternary logic has increased the accuracy also. In this work HSPICE is used for compilation & simulation purpose. Architecture used in this is pipelined ADC with resolution of 4 digits. Stanford University CNTFET model developed by Stanford nanoelectronics lab was being used. Power dissipation of this A/D converter was found to be 0.3mWatts. Page 2 of 2

Title: Traffic light controller using Verilog

HDL:Verilog

EDA tool: Xilinx ISE, Modelsim

Duration: February 2013-April 2013

Description: In this project, Xilinx SPARTAN 3 kit was used. This FPGA was programmed for real time traffic signaling system using Verilog. Verilog code was simulated using modelsim. Synthesis was done using Xilinx ISE 8.1. Functionality was tested using Spartan-3 kit. Title: Smart antenna system

Tool: MATLAB Simulink

Duration: August 2011-April 2012

Description: Smart antenna system is the innovative way to meet the growing demands of powerful, cost effective & high efficiency from wireless communication system. Smart antennas, when used appropriately, help in improving the system performance by increasing channel capacity and spectrum efficiency, extending range coverage. They also reduce delay spread, multipath fading, co-channel interference, system complexity, bit error rate. Area of Interest:-

RTL Design

Layout Design/Physical Design

Analog Circuit Design

ASIC

Design Verification

System-On-Chip

Co-curricular

o Organized Tech Crossword event at annual Technical festival of my college FERVOR 2011

o Participated in Industrial visit conducted by IETE student chapter to

“Control-room, western railway, Mumbai central”

Personal Information

Date of Birth: 19th August 1990

Nationality: Indian

Languages Known: English, Marathi, Hindi, Sanskrit

Interests: Music, Reading, Sanskrit shloka Pathan etc.

Strengths: Quick learner, Punctual, Hard worker. I hereby declare that above written particulars are true to best of my knowledge and belief. Place: PANVEL Aditya S. Gokhale

Contact this candidate