Yoav Karmon

NYC: +1-914-***-****, London: +442*********, Israel +972-**-*******, acqjea@r.postjobfree.com

Summary:

●Bachelor of Electrical Engineering, Ben Gurion University.

●Total of 10+ years of experience as FPGA and software engineer.

●Fluent in VHDL, C, knowledgeable in verilog.

●Fluent in, MODELSIM, QUARTUS, NIOSII, SignalTap and all Altera tools.

●Fluent 10G ETHERNET and communication.

●Experience with implementations of finance algorithms, Low latency design.

●Experience with exchange parsing and protocols: ITCH / OUCH / fix

●Experience with implementing 3rd party IP.

Education and professional training:

2009-2005: Studies to BS.c in electrical engineering university of Ben Gurion.

2008: software embedded systems programming course in - SOPC BUILDER.

2009: RT systems development on Linux. Including KERNEL and DRIVERS.

2011: FPGA DDR memories.

Professional specializations:

●Programming Languages: C, C++, VHDL, verilog,C#.

●Technologies /Architectures: IXIA, FPGA, NIOS2 systems (ALTERA), CPU design.

●Software: matlab, quartus, SignalTap, VisualDsp + +, SOPC Builder, ModelSim.

Experience:

2013/3 – Today: HFT trading company.

Description: development of FPGA & embedded software based trading platforms.

Hands on:

●Developing FPGA based /10Gbps trade algorithms for US market.

●ITCH/OUCH/Fix.

●Reducing risk in development,distributing work.

●Integrating FPGA for in-house work in reducing risk calculations in real time.

●Using FPGA to test real time latency of servers.

2010/1 – 2013/3: Sivron LTD.

Description: development of FPGA & embedded software based training platforms.

Hands on:

●Developing FPGA based 10Mbps/100Mbps/1Gbps/10Gbps network stack supporting UDP-MULTICAST, TCP, ICMP and more.

●FPGA based soft CPU design, real time software.

●FPGA based Low latency designs.

●Planning BACKPRESSURE mechanisms.

●Cut through architecture, compared to store & forward, Pipe-lining.

●Server/Client methodology on FPGA based systems.

●Low-latency DDR memory linked-list implementations on hardware.

●Low latency search algorithms over DDR using C + FPGA.

●Working with MAC AND PHY 1GHz, fast TRANSCEIVERS.

/ continued...

2005 – 2011/9: IAI

Hands on:

Planning and Upgrading 8 bit CPU to 32 bit (NIOS) in the FPGA.

project included implementation of new technology (a SOPC Builder)

STA verification: including using MULTI CYCLE, FALSE PATHS.

C2H algorithm on the FPGA, including the constraints of time \ frequency \ physical size \ power.

Building UARTS and communications components synchronizations and non-synchronizations, integrating processors.

Designing an ETHERNET from the Mac and UDP hardware, and TCP software on the FPGA.

Design and system integration of reconfigurable FPGA using ETHERNET and FLASH cards.

Implementation of image processing algorithms, and filter noise, sound and video.

●Programming test plans, and implementation of algorithms.

●Programing RT code to create signal generators, control of communication.

●Programming C code for control performance of RAM and systems..

●Planning TFTP file transfer and self-configurable FPGA.

Languages: Fluent in Hebrew and English.

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