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Digital design, verilog HDL, CMOS VLSI

Location:
India
Salary:
as per industry schedule
Posted:
July 02, 2015

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Resume:

RESUME

PRATHIBHA RADDER

#****, **** *****, **** ********* petrol bunk, ring road, banashankri 2nd stage, Bangalore-70

Email id: acqj5f@r.postjobfree.com

Contact no: +919****-*****

Career Objective

To seek a challenging and career oriented job, which enables me to update with the emerging latest Technology and provides scope for widening the spectrum of my knowledge.

Qualification

Institute of Study

Specialization

Year of Passing

Score

Post Graduation

R V College of Engineering, VTU Bangalore

VLSI Design and Embedded Systems

2015

65%(as of 3rd sem)

Degree

Bellari Institute of Technology and Management, Bellary, VTU

Electronics and Communications

2013

71.23%

P.U.C

Vijaynagara PU College, Hospet

PCMB

2009

66.67%

S.S.L.C

Rastrotthana High School, Hagaribommanahalli

Karnataka State Board

2007

74.24%

Academic Credentials

Technical Skill Set

HDL :Verilog modelling of Digital circuits

Programming languages :C programming

Hardware tools :Cadence Spectre and ADE, Multisim Schematic, Xilinx virtex- 5

Simulators :Modelsim Altera 6.3g_p1 (analysis of Waveform)

Analog Design using Cadence Virtuoso 6.10 tools.

Academic Skills

Digital design

CMOS VLSI design.

Knowledge on cadence tools for analog and digital design

Projects

M.Tech project: Crosstalk minimization of SOC’S using NOC.

Tools used: Xilinx 14.2, Cadence SOC encounter for Synthesis, Verilog HDL

Description: A novel encoding technique is proposed in the work to reduce the switching activity and noise coupling capacitance in NOC. The switching activities is reduced by transmitting the data on the links with data causes minimum switching activity. The encoder and decoder are designed for the proposed scheme in RTL level in Verilog HDL.

M.Tech Mini Project: Design of an efficient 3bit and 4bit Flash ADC.

Tool Used: Cadence Virtuoso 6.10 tool

Description: A novel attempt is made to design low- power 3bit and 4bit ADCs. The design and Pre simulation are carried out in cadence environment using spectre simulator under 90nm technology. The pre simulation results for the design shows a low power dissipation of 87uw for the comparator and 1.05mW and 1.984mW power dissipation for 3-bit and 4-bit Flash ADC respectively.

B.E Project: Solar tracking agricultural pump.

Team size : 4 members

Tool Used : Keil IDE (microcontroller)

Description: In this project we use the solar energy for generation of electrical energy, by using the Solar cells. The solar panels which are being used generates electrical energy from natural resources like solar light. The sensors are provided to sense the wetness of the soil, if the wetness is less the pump will be automatically switched ON. The main advantage of project is that No attention is required if automated. The battery operates safe condition because of monitoring for its low and high voltage. photovoltaic power for irrigation is cost competitive with traditional energy sources for small,remote applications, if the total system design and utilization timing is carefully considered and organized to use the solar energy as efficiently as possible.

Workshop/Seminar:

Attended “Focus Academy for Carrier Enhancement” program at BITM college, Bellary.

Soft Skill Development course under Innovation Unlimited at BITM college, Bellary.

Participated in the workshop on “Verilog ” organized by RVCE, Bangalore..

Activities and Achievement:

Got 585 score in GATE 2013 exam, 2033 rank out of 256135 (54/100 marks)

NCC B-certificate holder.

Won several medals at school level sports.

Participated in science exhibitions at school level.

Personals Traits:

Gregariousness, Adaptability

Follow up, Proactiveness

Good analytic ability, Calmness

Declaration :

I here by declare that all the information mentioned above is true to the best of my knowledge.

Date:

Place: Bangalore (Prathibha.Radder)



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