OBJECTIVE : Passionate to learn new technologies and to excel innovative technology application. Seeking a challenging position which will enable me to continuously learn, create, innovate and simultaneously contribute to the short and long term goals of the organization effectively using my technological & managerial skills.

SKILLS SET :

EDA Tools : Keil, Xilinx ISE 14.7, ModelSim

Hardware Description Languages : Verilog

Software Skills : C, Perl, Bash.

Platforms : Ubuntu, Windows.

TECHNICAL EXPERTISE : ASIC & FPGA Flow, FPGA Based System Design, Low Power CMOS VLSI Design, Digital Design, Microprocessors, NoC, SoC, Faults In Digital Circuits.

EDUCATION:

High School from UP Board with 76.00 % .

Intermediate from UP Board with 65.40 % .

B.Tech (ECE) from JNTU Hyderabad with 63.81 % .

M.Tech (VLSI) from Galgotias University with 6.57/10 in 2015.

M.TECH PROJECT :

Design of low power reconfigurable NoC router.

There are four different channels in this router from where data can enter and leave .It can reconfigure itself depending on the amount of data.

If it is more than the stack height of FIFO of one channel the rest of the data is routed to its neighbouring channel depending on the availability of remaining block.

Used clock gating technique and one channel off and partially crossbar for reducing the power consumption.

Simulation on modelSim and Synthesis on Xilinx ISE and implementation on Spartan 6 FPGA (Xilinx).

Analysis of power by XPower Analyser (Xilinx).

ADVANTAGE : In this protocol I used WINDOWS 7 with XILINX ISE 14.7 .

B.TECH PROJECT :

Remote Controlled Scrolling Display Board

●The main purpose of the project work is to change the message through remote control unit.

● When the display system is interfaced with the computer, then with the help of keyboard, the message can be changed.

● Message can be generated through keyboard, and encoded message is transmitted is displayed.

● Information is fed to EEPROM for storing the data.

AREA OF INTEREST :

FPGA Design

Memory Design

ASIC Design

High Speed Digital Design

NoC Archtitecture Design

SoC Design

TRAINING :

3 months trainging in 3st technologies noida

6 months trainging in dkop lab noida

PERSONEL STRENGTH :

Hard working and good at team work.

Rapid at learning things.

Good Knowledge in the VLSI Design flow.

Strong analytical Ability Skills.

Basic Knowledge of Networking and Hardware.

Sincerity to complete the assigned tasks.

HOBBIES :

Playing cricket, Internet surfing, Listening songs.

PERSONEL DETAILS :

NAME MANISH KUMAR PANDEY

FATHER'S NAME YOGENDRA NATH PANDEY

DATE OF BIRTH 20 JULY 1987

MARITAL STATUS SINGLE

PASSPORT NO K3173802

DECLARATION : I hereby declare that all the information given above is true to the best of my knowledge and belief.

MANISH KUMAR PANDEY

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