GIBIN M. GEORGE MOBILE 966-***-****,779-***-****

Home Landline/M 940*******

Citizenship DOB:04/10/1989 Gender : EMAIL acpyfd@r.postjobfree.com

: INDIAN Male

Present Room no.108, 6th block, MIT Hostels, Manipal, Karnataka

Address

Permanent Mylakkattu (h), Puthuppally P.O., Kottayam, Kerala

Address

Objective To be part of an organization where I can utilize my technical knowledge

and skills

Educational Qualifications

Grade School / College Board / Duration (yr) % / CGPA

University

M. Tech Manipal Institute of Manipal 2 7.36

Technology, Manipal

B.Tech College of CUSAT 4 72.00

Engineering,

Kidangoor, Kottayam

12th Donbosco H.S.S., Higher 1 86.33

Puthuppally, Kottayam Secondary

10th Donbosco H.S.S., Kerala State 1 95.13

Puthuppally, Kottayam

Branch of Engineering ELECTRONICS & COMMUNICATION

Sem 1

M.Tech Branch : MICROELECTRONICS

CGPA : 7.36

Elective VLSI Physical design & Verification

Subjects VLSI Testing and Testability

Analog VLSI for Signal processing

Applied Linear Algebra

Areas of Digital VLSI design

Interest VLSI verification & validation

Analog & mixed signal design

Embedded systems

Signal processing

Skill Sets

Software Cadence Design Tool (Incisive, Encounter RTL Compiler & Virtuoso)

Modelsim

Xilinx ISE

MATLAB

Programming C

languages Verilog

System Verilog

VHDL

Verificatio UVM (basics)

n

Methodology

Scripting Python (basics)

languages

Protocols AMBA APB, I2C

known

Technical Activities

M.Tech Project : Design and advanced verification of ARM AMBA APB 3.0 using System

Verilog and UVM

Brief summary : AMBA APB 3.0 protocol was designed using memory controller as slave.

Hierarchical testbench environments were build using plain System Verilog and UVM to

verify the operations, basic write and read, burst transfer, write and read with wait

states. Functional coverage and assertions are included to measure the quality of

verification process. Cadence Incisive Tool was used.

B.Tech Project : Design and Implementation of I2C Master core using VHDL

Brief summary : I2C Master core was designed using VHDL and simulated in Modelsim

.Design was implemented in Xilinx Spartan 3 FPGA kit

Mini project : Design of low power carry select adder using verilog

Attended 6 - month training programme on Cadence Design Tool for Digital VLSI

design conducted by

Karnataka Microelectronics Design Centre (KarMic),Manipal

Attended in - plant training in Basic Telephony at BSNL, Kottayam

Attended workshop on Pattern Recognition conducted by CERD at RIT Kottayam

Industrial visit at KELTRON Controls, Aroor

Hobbies : Reading, travelling, playing badminton

Work Experience

Intern at Karmic Design Centre, Manipal (September 2014 - June 2015)

Project fellow in KSCSTE sponsored project -"Effect of mimicked speech on automatic

speaker verification system."( July 2012 to July 2013)

Achievements

Qualified GATE (Graduate Aptitude Test in Engineering)

Co-author in two publications

1. Leena Mary, Anish Babu K.K., Aju Joseph, Gibin M. George

" Evaluation Of Mimicked Speech Using Prosodic Features " Proceedings of International

Conference on Acoustics, Speech, and Signal Processing (ICASSP 2013),Vancouver,

Canada

2. Aju Joseph, Gibin M. George, Anish Babu K. K., Leena Mary

" Computation of Speaker Similarity using Phrase Level Prosodic Features " Proceedings

of National Technological Congress (NATCON 2013), RIT Kottayam pp. 112-115

References:

1.Prof. D.V Kamath, Professor, Dept. of ECE, Manipal Institute of Technology

Ph: 91-961******* (M), 082*-******* (O),Email: acpyfd@r.postjobfree.com

2.Prof.S.N.Bhat, Associate Professor, Dept. of ECE, Manipal Institute of Technology

Mob. No: 91-944*******,Email: acpyfd@r.postjobfree.com

The above information provided by me is true and have all the relevant documents to

authenticate the same.

GIBIN M. GEORGE

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