Panchavati Rooms

Near PESIT college, Banashankari 3rd stage

Bangalore -85

+919*********

acpw34@r.postjobfree.com

ARAVINDAN. J

OBJECTIVE I am interested in obtaining a development position, and to

deliver best of my knowledge and skills to company as per its

requirements and to grow and excel with team spirit along

with the company.

SKILLS & ABILITIES Familiar with Xilinx EDA tools, Verilog

Familiar with MATLAB. Simulink tools

Knowledge of C.

EDUCATION M.TECH (MICROELECTRONICS &CONTROL SYSTEMS) 2012-

2014

VISVESVARAYA TECHNOLOGICAL UNIVERSITY.

PES Institute Of Technology, Bangalore.

70%

Aggregate -

B. E (ELECTRICAL AND ELECTRONICS ENGINEERING) 2007-

2011

VISVESVARAYA TECHNOLOGICAL UNIVERSITY.

Sri Bhagawan Mahaveer Jain College of Engineering, Bangalore.

64.16%

Secured a First class degree with an aggregate of -

PUC 2007

Karnataka State Pre-University Board

St’ Aloysius Pre University College, Mangalore.

- 75%

Secured an aggregate of

SSLC 2005

KARNATAKA STATE BOARD.

Cascia High School, Mangalore.

- 76%

Secured an aggregate of

ACADEMIC PROJECTS

M.Tech Main Project : HIGH PERFORMANCE ADAPTIVE FIR FILTER SYSTEMS

DESIGN BASED ON FPGA ARCHITECTURES USING RLS ALGORITHM

In this project a high performance Adaptive FIR filter architecture is designed. In particular,

the Recursive Least Square (RLS) algorithm for adaptive signal processing is explored based on

QR decomposition, which is accomplished by using the Givens Rotation algorithm. The Givens

Rotation algorithm is implemented using CORDIC based architecture. These architectures are

suitable for high-speed FPGAs or ASIC designs. This system identification model is tested and

verified using the following 4-tap FIR filter. Error output between the desired signal and the input

signal is found using Matlab.

M.Tech Mini Project : Implementation of a Ling Adder.

In this project a 8 bit Ling Adder is designed, this is implemented in Xilinx ISE simulator and

it is further extended for 16-bit. The Logic Depth of the circuit is found.

B.E Project : Design And Fabrication Of Layer Conductivity Meter.

To check the uniformity of the pollution over the insulator we are in need of developing a

meter to check the conductivity of the insulator at different points so that we can achieve uniform

distribution of pollution over the surface of insulator. In our project work we have developed a

Conductivity Meter according to IEC standards, IEC Pub 507:1991, IS 8704 :1995.

PAPER PUBLISHED

"High Performance Adaptive FIR Filter Systems Design Based On FPGA Architectures Using

RLS Algorithm," International Conference on Recent Trends In Engineering Science And

Management (ICRTESM-15), 15th March, 2015, JNU, New Delhi.

• Good knowledge of CMOS fundamentals, Digital Systems.

AREAS OF

• Good Understanding of Static Timing Analysis.

I N T E REST

• Knowledge of VHDL / Verilog.

• Opted Testing & Verification of VLSI circuits, Neural Networks as electives

in M. Tech.

• Secured 90.60 percentile in GATE2011.

ACH I E VE M E N

• Active participation in “Author workshop national live WebEx by Keith

TS

Lambert”

• Solving Rubik’s Cube.

• Easily adapt to new technologies, Optimistic person.

STRENGT HS

• Good analytical and problem solving skills.

PERSONAL PROFILE Name : Aravindan J

D.O.B : 06-05-1989

Father Name : Jayaprakash P

Languages Known : English, Tamil,Kannada, Hindi,Tulu.

NATIONALITY : INDIAN

Permanent address : Karkera Garden,

Near Marigudi, Bolar,

Mangalore-575001

Karnataka

DECLARATION I hereby declare that all the information furnished above is true to

the best of my Knowledge and records available.

PLACE:

DATE:

ARAVINDAN . J

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