C URR ICU LAM V ITAE

AZRUD D I N ANSAR I

C/o Garib Nawaz Manzil, Behind of Match Factory,

D adwara, Kota Jn. M obile:

+917*********

Rajasthan E mail:

acpub2@r.postjobfree.com

CAREER OBJECT I V E:

Looking for the role of Design Engineer which requires applying my analytical skills in field of VLSI so as

to enrich engineering knowledge obtained and grow with the organization.

PROF I L E:

• Working as an Assistant Professor i n E lectronics & Communication Department a t C areer

Point University,

A laniya, Kota.

• Worked as an I N TERN in SION Semiconductor, Bangalore for one year .

• Masters in VLSI-CAD w ith 8.20 CGPA f rom M anipal University, Manipal.

• Basic knowledge of CMOS.

• Knowledge in Verilog based Test bench Development.

• RTL/Gate level simulation, RTL Synthesis and Debug.

• In depth knowledge in Digital Circuit Design Concepts and ASIC Flow.

• Ability to work in a team as well as an individual.

• PROFESSIONAL WORK EXPER I E NCE:

• I have six months working experience in University.

• I am holding a responsibility as an In-charge of Event Management Commit tee in Career Point

U niversity.

Project: An I nnovative Design of the DDR/DDR2/DDR3 SDRAM Compatible Controller

(SION Semiconductor)

Our challenge going forward is to continue to increase system performance by

Synopsis:

narrowing the performance gap between processors and memory. If we compared

D DR2 with DDR3 then i t is designed to run at lower power, higher memory speeds the

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signal integrity of the memory module. Based on a common standard bus interface, an

i nnovative design of the DDR/DDR2/DDR3 SDRAM compatible controller is

i mplemented. This memory controller maximizes channel bandwidth, more f lexible,

t ransplantable and minimizes access latencies through efficient request scheduling,

i ntelligent refresh schemes.

Understanding DDR design of M icron sheets technology and according with that wri te

Responsibilit

t he testbench code to meet the t iming challenges for controller.

y:

Verilog, Modelsim, Questasim (Mentor Graphics)

Language,

Tool:

• T EC H N ICAL SK I L LS:

Verilog, System Verilog

H a rdware Description Language:

Modelsim, Questasim, VCS

Tools:

Magic, BSpice

Model Simulator:

Design Compiler (Synopsys)

Synthesis:

• ED UCAT IONAL QUAL I F ICAT IONS:

C lass/Course Name of I nstitute Board/Universit Year of Grade

y P assing

MS Manipal Center for Manipal 2012 8.20 CGPA

(VLSI-CAD) I nformation Science, U niversity

M anipal

BE Modi Institute of University of 2009 67.5%

(Electronics and Technology, Kota Rajasthan

Communication)

• MASTER’S PROJECTS:

P roject: An Embedded T rue Random Number Generator for FPGAs in VER I LOG

Field Programmable Gate Arrays (FPGAs) are an increasingly popular choice of

Synopsis:

p latform for the i mplementation of cryptographic systems. Until recently, designers

using FPGAs had less than optimal choices for a source of t ruly random bits. I t

p roduces random bits at speeds of up to 0.5 M bps w ith good statistical

characteristics.

Understanding of the design behavior and FPGA Concept and i ts

Responsibili

i mplementation in terms of Verilog. Development of Verilog based Test bench to

ty:

verify the design by wri ting number of test cases.

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Verilog (Modelsim), VCS (Synopsys)

L anguage,

Tool:

Project: Arbiter(under “WH IZCH I P TECHNOLOGY” Bangalore)

Arbiter facilitates the connection between master and slave for proper

Synopsis:

communication. MASTER and SLAVE is a model of communication where one

device or process called Master has unidirectional control over one or more devices

called Slaves. In this project a MASTER is elected from a group of eligible devices,

w ith the other devices acting in the role of slaves.

Understanding of Master-Slave concept and the implementation of Arbiter

Responsibilit

design in Verilog. Development of Verilog based Test bench to verify the Arbiter

y:

design by wri ting number of test cases of master-slave scenarios and arbiter cases.

Verilog (Modelsim), VCS (Synopsys).

Language,

Tool:

Project: Universal Asynchronous Receiver and T ransmitter (UART)

UART, In the asynchronous t ransmission the data is not sending at all t imes.

Synopsis:

W hen no data is send the line remains in the High state. When the data is to be

t ransmit ted then the Low s tart bit is sent before the data byte and the receiver

detects that bit and accepts the data byte. A t the end of the data a H igh stop bit is

send which tells the receiver that the data byte is ending here.

Understanding of the UART Protocol and its implementation in Verilog. Development

Responsibili

of Verilog based Test bench to verify the UART implementation.

ty:

Verilog (Modelsim), VCS (Synopsys).

Language,

Tool:

• GRADUAT IO N PROJECT:

P roject: Maglev T rain

The project based on the working principal of repulsion mechanism of magnets. The

Synopsis:

basic mechanism behind propulsion of the t rain is called Hall Effect, for this we have

used hall sensors with an electromagnet. Two parallel t racks are made up by

permanent magnets, same kind of magnets are used at the side end of the t rain

(bottom). An electromagnet is used with a hall sensor in the center bottom side of the

t rain. Here I use M icrocontroller 89C52.

Understanding of project aspects like hall sensors. Electro-magnets concepts and

Responsibili

mount the whole circuit on PCB.

ty:

Visual Basics, M icrocontroller 89C52

Tool:

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• EXTRA-CURR ICU LAR ACT I V I T I ES:

• Successfully organized various events like “ NAMBARDAR Live Concert”, “Ek Shaam Dr.

K umar Vishwas Ke Saath” a t CP Tower as a coordinator of event management commit tee in

Career Point University, Kota.

• Done a M ini project on “ Traffic Light Controller” i n M IT, Kota.

• Member of Editorial Board of College.

• Member of school Cricket team.

• Secure good position in Bhartiya Sanskri ti Gyan Exam.

• Qualified the NASSCOM Assessment of Competence (NAC).

• SEM I NAR D E L I V ERE D:

• Gave seminar on M oletronics i n M C IS, Manipal University, Manipal .

• Gave seminar on S kinput Technology i n M C IS, Manipal University, Manipal .

• Gave seminar on H aptic Technology i n M IT, Kota .

• HOBB I ES:

• Listening music, playing and watching Cricket.

• Playing Chess, Carrom.

• Reading religious books.

• PERSONAL DETA I LS:

Name : Azruddin Ansari

Father’s Name : Late Fakhruddin Ansari

L anguages Known : English, H indi, and Urdu

P lace : Kota

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