Rajani.Inja

Contact: 903-***-****/acpq1r@r.postjobfree.com

Professional Summary:

> Having 3 years of total industrial experience.

> Worked as a FPGA Design Engineer for a duration of 2 years 11

months in Accord Software and Systems Pvt. Ltd., Bangalore.

> Experience in developing a design using VHDL,Verilog.

> Handle design, development, testing and debugging of the application.

Educational Qualifications & Achievements:

> M.Tech in VLSI Design from Guru Gobind Indra Prastha University CDAC,

Nodia with 76% in 2012.

> B-Tech in Electronics & communication Engineering from MIC of colleage of

Technology,AP with 82% in 2010.

> INTERMEDIATE from BOARD OF INTERMEDIATE EDUCATION, AP with 96% in 2006.

> SSC from SCHOOL OF SECONDARY EDUCATION, AP with 87% in 2004.

> Stood as the topper in my branch in academics.

Technical Skills:

EDA Tools : Xilinx Vivado, Xilinx ISE

14.6, Altera Quartus II, Matlab

Simulation Tools : Xilinx ISim, Modelsim

Debug Tools : Vivado Logic Analyzer and

Chipscope

Programming Languages : VHDL, Verilog, C

CPLD/FPGA Micro controllers : Xilinx FPGAs(Spartan 3, Spartan 3E,

Spartan 6,Virtex 4,

Virtex5, Virtex6, Zynq,

Artix 7), Altera FPGA, 8085 & 8086

Microprocessor, 8051

Micro-Controller

Familiar IP /cores : Xilinx(BRAM), DCM, DSP Slice,

ROM, DDR2, DDR3, FFT

Familiar OS : MS Windows

Avionics Industry Standard : DO-254

Work Experience:

Organization : Accord Software Systems Pvt. Ltd., Bangalore

Jul 2012 - Till Date

Role : Sr. Systems Engineer [FPGA Design Engineer]

Department : GNSS & Aerospace

Project 1 : All In View Receiver

(GPS, GLONASS, IRNSS, SBAS, BEI-DOU, GALEILEO, QZSS)

Language : VHDL

Development & Simulation Tools: Xilinx 14.6, Vivado 2014.4

Project Description:

This a development project. AIV Receiver is used to find the very accurate

position of user.

Responsibilities :

> Designing and Implementing synthesizable RTL code.

> Integrating all the RTL modules for acquisition process.

> Writing test bench to verify design functionality and Timing.

> Validating the design on the hardware.

Project 2 : ATDL Project (L3-

ACSS Project): Air Transport Data Link Layer

Development and Simulation Tools : Xilinx ISE 12.2

Language : VHDL

Project Description:

This is a Verification and Validation (V&V) project.

Responsibilities :

> Designing and Implementing the efficient test benches for the given

RTL code.

> Integrating all the TB modules.

> Writing the top level test bench to verify design functionality

requirements and timing

requirements.

> Validating the design requirements: The top level test bench invoke

the sub-test benches by reading the commands written in the script

file (text file) then validating all those commands corresponding to

the design requirement document.

Project 3 : Simulator Project

Development and Simulation Tools : Xilinx ISE 12.2, Xilinx Isim

Language : VHDL

Project Description:

This is a Research and Development (R&D)

project at Accord. The signal generated through the simulator project is

considered as an input to all the receiver projects. Based on this,

position, height and angle of the user is determined.

Responsibilities :

> Designing the Simulator project.

> Implementing the synthesizable RTL code for all the designed modules.

> Designing efficient test bench to verify design functionality.

> Testing the design functionality by using test bench and then

validating the results.

> Generating the bit stream with proper user constraint file (ucf file).

> Checking the timing analysis (STA) report: setup and hold time check.

> Gate Level Simulation.

> Validating the design on the hardware.

Project 4 : IRNSS Receiver Project

Development and Simulation Tools : Xilinx ISE 13.3, Xilinx Isim

Language : VHDL

Project Description:

In this project the accurate position and the rate of motion (velocity) of

the user is determined by acquisition and tracking methods.

Responsibilities :

> Designing the IRNSS Receiver project.

> Implementing the synthesizable RTL code for all the designed modules.

> Designing efficient test bench to verify design functionality.

> Testing the design functionality by using test bench and then

validating the results.

> Generating the bit stream with proper user constraint file (ucf file).

> Checking the timing analysis (STA) report: setup and hold time check.

> Gate Level Simulation.

> Validating the design on the hardware.

Project 4 : Implementation of Sub-Modules

Development and Simulation Tools : Xilinx ISE 14.6

Language : VHDL

Project Description:

1. Implementation of memory modules.

2. Implementing and testing of inference code of IP cores (DSP Slice).

Acadamic Projects:

M. Tech. Project 1:

Project Title : Development of Radix-2 based 1024-point FFT

Implementation

Project Description :

The 1024-point FFT (both Decimation in Time (DIT) and Decimation in

Frequency (DIF)) is designed and implemented. The Radix-2, Radix-4 and

Mixed Radix based FFT is implemented. The efficient test bench is written

to test the design functionality and timing requirements.

Platform: Mat LAB R2010a, VHDL

Duration: 5 months

Organization: Accord Software Systems Pvt. Ltd, Bangalore.

M. Tech. Project 2:

Project Title : Design and Analysis of Sense Amplifier Based Flip

Flop

Project Description:

To minimise the delay between the latest point of data arrival and output

transition in Flip-Flops. In order to reduce this delay in Flip-Flops,

sense amplifiers are used to design the Flip-Flops. Typical representatives

of these structures are Sense amplifier based Flip-Flop(SAFF),Transmission

Gate Master-Slave Flip-Flop(TG-MS FF),C2MOS Master Slave Flip-Flop(C2MOS

MS FF).

Platform : Tanner EDA, IC Station

Duration : 5 months

Organization : CDAC, Noida.

B. Tech. Project 1:

Project Title: Development of GSM Based Moving Message Display

Project Description:

To design and develop moving message display board with GSM as source for

messages. The designed Scrolling Message Electronic Board displays the

large amount of information received as SMS in different bright colours. No

distance barriers will be there and hence provides full flexibility to the

user to operate the display board from anywhere within sections.

Platform: Assembly Language

Duration: 5 months

Organization: MIC Technology, Hyderabad.

Personal Skills:

> A pleasant personality with strong analytical, good communication and

presentation skills.

> Responsible, Reliable and Self-starter.

> Respond positively to a challenge with patience and tolerance.

Achievements:

> Placed 1st in academics at school and college level and won the best

outgoing student award.

> Got good Eamcet and Gate score without attending the training programme

Co-Curricular Activities:

> Presented a seminar on "Visual Light Communication System".

> Presented a project on "Audio communication using FO cables" at national

level project exhibition contest held at MIC College of Technology.

> Attended the workshops "Field Programmable Gate Array" and "Programmable

SoC" held at IIT Delhi.

Extra Curricular Activities:

> Organized event called "National Level Technical Paper Contest in

Aagama'08 held at MIC College of technology.

> Organized event called "VLSI and Embedded systems quiz" in Technofest'09

held at MIC College of technology.

> Volunteered events in cultural fest held at MIC College, JNTU University.

Personal Details:

Father's name : Obula Reddy.Inja

Date of Birth : 06-07-1989.

Hobbies : Listening to Music, Gardening.

Address : D/O.I.Obula Reddy, Sri Sai Ladies PG, 330/3,3rd

Main,7th Cross, Domlur Layout, Bangalore-60071.

Languages Known:English, Hindi, Telugu and Kannada

Declaration:

I hereby declare that the above written particulars are true to the best of

my knowledge and belief.

Date:19-05-2015

(RAJANI.I)

Place: Bangalore.

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