ANTHONY T. MOORE

**** ********* **** ****** ******, Texas 75252

H 972-***-**** C 214-***-****

acpfh7@r.postjobfree.com

SUMMARY

A detail-oriented and analytical electrical engineer with a

demonstrated track record of achievement in root cause/electrical

failure analysis, qualification testing, test program creation, scan

chain failure debug/analysis, and yield enhancements. Established

capabilities in continuous improvement, diagnosis support, and

flows/procedures. Adept at researching, analyzing, and documenting

technical data. A reliable self-starter with a history of

prioritizing heavy workflow with competing and overlapping deadlines

to ensure quality outcomes.

. Semiconductors

. Defect Source Analysis

. EFA/DFT Methodology

. Flow/Procedures

. Planning/Strategy/Tactical Execution

. U.S./Global Resources Trained

TECHNICAL SKILLS

ATPG Tools: Mentor FastScan, Synopsys TetraMax, Cadence Encounter Test

Hardware Design Software: Mentor Design Capture, Gerbtool/PCB Viewer,

schematic verification

Software: Knights CAD, Inovys Stylus, Microsoft Office Suite

EXPERIENCE

TEXAS INSTRUMENTS Richardson, Texas

Product Engineer 2005-2014

. Planned and executed Electrical Failure Analysis activities to drive

root cause analysis and corrective actions for Digital Signal

Processing System products.

. Created load board designs, test programs, and solutions while

developing data failure logs and utilizing scan diagnosis to isolate,

contain, and eliminate defect sources in manufacturing flow process.

. Worked with cross-functional teams to resolve critical issues related

to quality and reliability.

. Prepared weekly reports for management review on yield and product

engineering.

. Served as technical lead focusing on scan diagnostics, load board

design, yield, test, customer returns, and logic failures for DSPS

group.

. Developed diagnostic solutions for hardware and scan-based test

software for 50 designs.

. Contributed to business growth of DSP Systems portfolio.

. Reduced burn-in by 3% for group of cell phone communications

infrastructure products.

. Increased yield by 5% through working with cross-functional teams to

reduce cold temperature failures.

. Led development and deployment of precision diagnosis solution and

drove evaluation of Inovys Personal Ocelot, desktop tester of choice

for silicon validation and debug.

. Mentored and trained team members in Houston and Dallas on Inovys

execution and debug techniques.

. Devised first fully cross-mapped Knights database with flow

requirements for LEF/DEF conversion.

. Analyzed low-yield materials, monitored/created test yield reports,

and reduced test times on products.

Design for Test Engineer 2002-2005

. Provided product and test solutions from product definition through

planning, production, and release to reduce product development cycle

time while improving test quality results.

. Served in mentorship role with other engineers while developing new

test techniques, technical specifications, and related reference group

documentation.

. Provided continuous improvements for design, test, and process

diagnosis activity for WLAN group.

. Acted as project lead on evaluation of Inovys' desktop tester, solving

yield and reliability issues as part of team effort, and functioned as

technical lead for scan diagnostics and electrical failure analysis

for logic fails.

ADDITIONAL EXPERIENCE

INNOSYNC, INCORPORATED, Dallas, Texas, Design For Test Engineer, 2001-2002.

Recruited for start-up design house for fabless chip company as one of 15

original engineers in design group focusing on USB design-based

connectivity chips. Utilized ATPG tools for scan diagnosis of top-level

designs with Mentor FastScan to determine stuck-at-fault coverage while

generating ATPG test patterns. Performed scan and boundary scan insertion

on Verilog netlist and created Test Description Language files for product

engineering, using Automated Test Program Generation tools.

ST MICROELECTRONICS, INCORPORATED, Coppell, Texas, Design For Test

Engineer, 1996-2001. Functioned as primary liaison between design and

testing groups. Planned and executed DFT methodologies, flows, and

procedures, from design phase through ATPG testing. Developed DFT flow

creation and tools to support internal Built-In-Self Test tools. Partnered

with cross-functional teams, including design, manufacturing, quality,

testing, technical support, and other engineering groups to achieve

rigorous goals.

SGS Thompson, Carrollton, Texas, Senior Test, Product Engineer, 1986-1996.

Worked with design and process engineers to develop CMOS SRAM products.

Monitored yield reports for various products and analyzed low-yield lots.

Managed product and test engineering for Mostek's Starlan Hub chip.

EDUCATION

UNIVERSITY OF PHOENIX, Dallas, Texas, M.S., Accountancy, 2012

NORTHEASTERN UNIVERSITY, Boston, Massachusetts, B.S., Electrical

Engineering, 1982

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