H.M. SRUJANA

hmsrujana**

@gmail.com

Verification Engineer Mobile No: 088********

Objective:

I want a challenging career where I can enhance my knowledge which I contribute to my organization. I am

creative and want to implement new ideas.

Academic Qualification:

Year of

Sl Course Institute Board/University Percentage

Pass

B.Tech Nova College of 80%

1 JNTUH 2013

Engg. &Tec

Intermediate Masters Junior

2 Board of Intermediate 2009 90%

(MPC) College

St.Johns English Board of Secondary

3 SSC 2007 84%

Medium School Education

Diploma Course:

Completed Training in Advance Diploma in ASIC Design for 6 months (July 2014 to January 2015) in

RV VLSI Design Center.

Skills and Abilities:

Hardware description languages : Verilog, System verilog,VHDL

Pre_silicon RTL verification experience in the linux environment

•

Strong problem solving and debugging skills

•

Familiarity with the ASIC design flow,including synthesis and timing closure.

•

Methodology : UVM

Programming Languages : C,C++

Scripting language : Perl

Tools /simulators : Mentor Questasim, Xilinx ISE, Matlab.

Others : Make files

Strengths:

Creative, Enthusiastic, Well organized and able to get along well with people. Completing the

assigned work within the time bound factor successfully.

Ability to work independently or as a part of team, Ability to understand, grasp, focused and

hardworking.

Achievements:

Participated in debate competition in CIRE(A Govt. of India Entrepreneur) and stood 2nd

I stood 1st in the elocution competition conducted by Nova College of Engg. & Tech .

I stood first in paper presentation conduct on the topic “H264” in Nova college of Engg

&Tech.

Participated in robotic challenge conducted by IIT Bombay in collaboration with

Robosepine.

Key Projects:

Project # 0

Project Name : Functional verification of mini UART protocol

Duration : 1 month

Environment : Linux

Language Used : UVM methodology

Description : Functional verification of mini UART protocol by developing code for self checking

test bench.

Responsibilities :

• Test plan creation from specification, Developed all test bench components like interface,

sequences, sequencer, input Driver, input Monitor, input agent, output agent, output

driver, output monitor, configuration database, Scoreboard, Environment, Test and Top

modules for mini UART DUV, regression testing with different corner cases and random

cases.

• Used latest tools to collect, analyze design and augment the test plan to achieve 100%

coverage.

Project # 2

Project Name : Functional verification of FIFO protocol

Duration : 15 days

Environment : Linux

Language Used : UVM methodology

Description : Functional verification of FIFO protocol by developing code for self checking test

bench using system verilog.

Responsibilities :

• Test plan creation from specification, Developed all test bench components like interface,

sequences, sequencer, input Driver, input Monitor, input agent, output agent, output

driver, output monitor, configuration database, Scoreboard, Environment, Test and Top

modules for FIFO DUV, regression testing with different corner cases and random cases.

• Used latest tools to collect, analyze design and augment the test plan to achieve 100%

coverage.

Project # 3

Project Name : Functional verification of mini UART protocol

Duration : 15days

Environment : Linux

Language Used : System Verilog

Description : Functional verification of mini UART protocol by developing code for self checking

test bench.

Responsibilities :

• Test plan creation from specification, Developed all test bench components like Generator,

Driver, Monitor, Scoreboard, Environment, Test and Top modules for mini UART DUV,

regression testing with different corner cases and random cases.

• Used latest tools to collect, analyze design and augment the test plan to achieve 100%

coverage.

Project # 4

Project Name : Functional verification of FIFO protocol

Duration : 15 days

Environment : Linux

Language Used : System Verilog

Description : Functional verification of FIFO protocol by developing code for self checking test

bench using system verilog.

Responsibilities :

• Test plan creation from specification, Developed all test bench components like Generator,

Driver, Monitor, Scoreboard, Environment, Test bench and Top modules for FIFO,regression testing with different corner cases and random cases.

• Used latest tools to collect, analyze design and augment the test plan to achieve 100%

coverage.

Project # 5

Project Name : Functional verification of RAM

Duration : 15 days

Environment : Linux

Language Used : System Verilog & verilog

Description : Functional verification of RAM by developing code for self checking test bench

using system verilog & description and did a comparative study between system verilog and

verilog.

Responsibilities :

• Test plan creation from specification, Developed all test bench components like Generator,

Driver, Monitor, Reference Model, Scoreboard, Environment, Test bench and Top modules

for RAM, regression testing with different corner cases and random cases.

• Used latest tools to collect, analyze design and augment the test plan to achieve 100%

coverage.

B.Tech Projects:

Mini Project:

Power optimization of LFSR using bist circuit.

Description: This is a project for verification of code in which test vectors are generated by

the circuit itself.

Main project:

Radix 8 booth encoded modulo 2n 1 multipliers with adaptive delay for high dynamic range

residue number system.

Description: This is a project to reduce the delay in arithmetic operations, which can indeed

increase the processor speed.

PERSONAL DETAILS:

Father’s name : H.M. Yesuratnam

Date of birth : 01 06 1991

Gender : Female

Marital Status : Married

Nationality : Indian

Languages known : Telugu, English, Hindi, kannada

:

Present address H.No 57 1, Taj unnisa building,

3rd floor,3rd cross,8th A Main,

BTM 1st stage,Bangalore 560029

DECLARATION:

I hereby declare that the information furnished above is true to the best of my knowledge and

belief.

Place: Bangalore (H.M SRUJANA)

Contact this candidate