GUNA SKANTHARAJAH

www.linkedin.com/in/gunaskantharajah

**** ******* ***** 416-***-****/610-***-****

Whitehall, PA 18052 acp88b@r.postjobfree.com

HIGHLIGHTS OF QUALIFICATIONS

Expertise in Digital ASIC/FPGA design/simulation/synthesis and Microcontroller design

Experience with electronic design methodologies using state machines (ASM/FSM) and algorithms

Experience with Low power digital design and power aware design/simulation using UPF and MVRC/MVSIM

Strong knowledge and experience with FSM design, multiple clock/voltage domains and pipeline processor architecture

Experience in Analog Behavioral Modeling (ABM) of PLL and IO pads

Hands on experience in ABV (Assertion Based Verification) based RTL design

Experience in Clock Domain Crossings (CDC) check and implementation of synchronizers, FIFOs and MUX recirculation

Experience with PCIe and AXI bus protocols

In-depth knowledge of RISC and CISC architecture gained through the design/simulation of High Performance vector/superscalar pipelined processors

Hands on experience with digital, analog and mixed signal ASIC layout, Floor planning, matching, reliability budgeting, P&R and DRC, LVS verification using Cadence Virtuoso 90nm technology

A challenge driven team player that works well in autonomous and group settings

Well-developed analytical, problem solving and time management skills

PROFESSIONAL EXPERIENCE

UPF Engineer (consultant) INTEL, Pennsylvania, USA 2014- 2015

Verified power architecture using MVRC on SOC level netlist (placement of level shifters, isolation cells, retention registers, power switches and buffers) for mobile communication SOC

Debugged Gate-level netlist using MVSIM (power aware simulation for functional verification)

Updated and generated UPF for several IPs

ASIC Design Engineer 2 AMD Canada, Markham 2012- 2014

Developed synthesizable and behavioral RTL codes for various modules including GPIO, SDIO, Temperature monitor, system control, clock generation and PLL blocks for GPU/APU

Designed, simulated and synthesized IO pads and PLL blocks in a mixed signal environment

Performed functional verification of several IPs and SOC by debugging, implementing system verilog assertions (SVA) and functional coverage

Implemented low-power design techniques such as clock-gating, power-gating, voltage and frequency scaling and FSM state encoding

Defined constraints for Synopsys DC, primetime and Mentor’s 0-in

Generated UPF files to run power aware simulation

Verified Clock Domain Crossings

Embedded OVL assertions and performed lint checks

Field Application Engineer NCR Canada Limited, Toronto 2006-2007

Designed, simulated, and synthesized FPGA's including Xilinx Spartan2

Designed and simulated 32-bit pipelined processor.

Developed schematics for motor control applications.

Field Engineer NCR Canada Limited, Toronto 1999-2006

Installed, commissioned, tested and troubleshoot various NCR products such as Automated Teller Machines, Optical Character Recognition and Image Processing Equipment at customer sites

Resolved technical issues in timely and effective manner by taking ownership of customer requests

Conducted research study for the improvement or reconfiguration of systems or sub systems

TECHNICAL SKILLS

EDA tools, s/w, h/w: VCS, ModelSim, MVSIM, MVRC, UPF, Synopsys DC, Equivalency checker LEC, Mentor’s 0-in CDC checker, version control software Perforce & Clearcase, static timing analysis (Primetime), Leonardo Spectrum, Xilinx WebPack ISE, Code Composer Studio (CCS), Mat lab, Code Worrier, Cadence Virtuoso ASIC layout tool, VHDL, Verilog, Assembly languages, C, Perl, OVL, system verilog, ARM, AHB AXI bus, PCIE, Fault tolerant systems design

Lab Test Equipments: Oscilloscope, Logic Analyzer, Signal generator, Multi meter

EDUCATION AND PROFESSIONAL DEVELOPMENT

Post graduate diploma in Applied Electronic Design

Seneca College, Toronto, Ontario

Special Student, Graduate Studies (MEng.)

Department of Electrical and Computer Engineering, University of Toronto

Graduate in Electronic Engineering

Council of Engineering Institution, London, U.K

Bachelor of Science (Mathematics)

University of Jaffna, Sri Lanka

PROFESSIONAL AFFILIATIONS

Eligible for PE registration in Ontario, Canada

Eligible for CEng in UK

Graduate Member of the Institution of Electronic and Radio Engineers, U.K.

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