MOHAMMED MUSAB

I am looking for an opportunity in academics that fully utilizes my technical skills towards

the growth of the organization through continuous learning and hard work.

Research Interests:

Low power VLSI systems, Digital system design and Physical design implementation.

Research Experience

1 year hands on experience in EDA tools.

Educational qualification:

M.Tech in VLSI Design and Embedded Systems (Progress) 2015

VTU Extension Centre, UTL Technologies ltd. Bangalore, VTU Belgaum (62%)

B.E in Telecommunication Engineering 2013

Atria Institute of Technology, Bangalore. Affiliated to VTU Belgaum (62.4%)

Diploma in Electronics & Communication Engineering 2009

RNS Rural Polytechnic, Murdeshwar (Karwar Dist.) BTE, Bangalore (64.07%)

S.S.L.C 2006

Savithri Convent HP & High School, Mysore. KSEE Board (78.4%)

Course Work: CMOS VLSI design, SoC, ASIC design, Digital system design using Verilog,

Physical design of VLSI circuits and Low Power VLSI design.

Technical Skills:

Programming Languages: Verilog HDL, Basics of C, C++.

OS: Windows & LINUX

Packages: MS Office, Xilinx FPGA design suite, Adobe Photoshop, hardware/software

Installations

Functional Simulations: Xilinx ISE 14.1, Modelsim

Tools used: Cadence encounter RTL compiler RC 9.1, Cadence NCSIM simulation

10.2, cadence Encounter.

Publications:

The paper titled "Study & Implementation of multi-VDD power reduction

technique", written based on the project work has been presented in the

proceedings of "IEEE international conference on computer communication

and informatics. ICCCI-2015"at SSIET, Coimbatore, India.

+91-998******* email: acp68k@r.postjobfree.com

MOHAMMED MUSAB

Project work:

1. Title: Study and implementation of multi-VDD power reduction technique

Advances in VLSI technology has led to design of complex circuits, these Complex circuits

consumes high power. Several traditional methods such as power gating, clock gating, multi

VT, variable VT etc., exits to reduce power dissipation. From the experimental results, Multi

VDD technique reduces the power by 85.83% when compared with single VDD.

Task: Multi-VDD power reduction technique for ISCAS89 S38417 benchmark circuit.

Challenges: timing analysis, fixing violations

2. Title: Low power design using multi Vdd technique

Design for low power requirement has become a key requirement in today’s SOC design; an

effective low power technique in designing System on Chip is to partition the design into

multiple power domains which operates at different VDD. The scope of the project is to

implement multi VDD technique for given CMUDSP benchmark circuit using cadence RTL

compiler with common power format (CPF).

Task: operating critical blocks of the SOC at higher voltages with lower power dissipation

using Multi-VDD technique.

Challenges: creating a bi-directional level shifters

Professional Training and Seminars:

Attended Workshop on Nano-technology and sensors at IISC, Bangalore

Attended Workshop on STUD-SAT at AIT, Bangalore

Attended Workshop on Embedded Systems at AIT, Bangalore

Hardware & Networking course at IICT, Bangalore

Attended Photonics conference organized by UTL technologies ltd., Bangalore

Attended Workshop on Design & Reuse IP SoC India 2015, Marathalli, Bangalore

Attended Workshop on Physical design Implementation organized by UTL

technologies ltd., Bangalore

Awards/Honors:

Secured second prize in BRV Vardhan paper contest conducted by IEEE Bangalore

section BMSCE 2015.

Won first prize in quiz, debate and Quran recitation competition during school days.

Volunteered in literary fest of 'AIT’ during bachelor’s degree.

Won second prize in project exhibition, essay writing and drawing competition.

Lead school, college, club cricket team and won many accolades.

Active participation in School and College Cultural activities.

+91-998******* email: acp68k@r.postjobfree.com

Contact this candidate